Broadcom Corporation

Chenmin Zhang

Vafa James Rakshani

Lawrence John Madar, Iii

Vinay Bhasin

Zhiqing Zhuang

Jalil Fadavi-Ardekani

Mark David Rutherford

Walid Nabhane

Steve Thomas

David Chang

Sam H Liu

Chaoyang Zhao

Narayan Prasad Ramachandran

Ajmal A Godil

Randall Stolaruk

Yi Ting Chen

Soheyla Kamal, Legal Representative

Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.

Charger detection and optimization prior to host control

Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

Method and system for advance high performance bus synchronizer

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external 'wake up event', will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Method for managing and controlling the low power modes for an integrated circuit device

Aspects of the invention provide a method and system for a communication bus for resetting one or more devices connected to the bus. The transceiver bus () may include a single serial data line (), a single serial clock line () and a single reset line (). A status of a slave device coupled to the transceiver bus () may be determined by a master device. Based on the status of the slave device, the master device may execute a forced reset or a normal reset. In a case where a device may be unresponsive, the master device may execute a forced reset. Additionally, in a case where a device is responsive but requires resetting, the master device may execute a normal reset and selectively reset a slave device requiring reset.

Method and system for a three conductor transceiver bus

Growing community of inventors

Irvine, CA, United States of America

Chenmin Zhang