Intel Corporation

Lsi Corporation

Agere Systems Inc.

Chengzhou Li

Kameran Azadet

Albert Molina

Meng-Lin Yu

Deepak Kataria

Ximing Chen

Herbert B Cohen

Joseph Williams

Bruno Jechoux

Jian-Guo Chen

Joseph H Othmer

Jinhui Li

Steven Pinault

Chunhui Liu

Ramon Sanchez Perez

Noy C Kucuk

Evstratios Vandris

In an example, there is disclosed an apparatus, having: a first network interface, having a first clock and a local communication driver to communicatively couple the first network interface to a second network interface having a second clock; and one or more logic elements, including at least one hardware logic element, providing a synchronization engine to: send a first plurality of data words from the first wireless interface to the second wireless interface via the local communication driver; receive back from the second wireless interface a second plurality of data words; assign a plurality of error rates to the data words of the second plurality of data words, the plurality of error rates indicating match or mismatch; identify a range of least error values within the plurality of error rates; and select an agreed baud rate from within the range.

Self-adapting baud rate

Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xfunction, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Software digital front end (SoftDFE) signal processing

A scheduler having improved throughput is disclosed, for scheduling packets or other data blocks for transmission from a plurality of transmission elements in timeslots in a communication system. The scheduler determines for the transmission elements respective channel capacities, and adjusts one or more of the channel capacities based on amounts of data available to transmit in the corresponding transmission elements. The scheduler then selects one or more of the transmission elements for scheduling in a given one of the timeslots based on the one or more adjusted channel capacities. The scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of the communication system.

Scheduling methods and apparatus based on adjusted channel capacity

A buffer memory is provided that comprises a plurality of memory elements for storing data elements in an order of arrival, wherein the plurality of memory elements have a variable size and wherein each memory element comprises a pointer (such as a next block starting index) to a memory element storing a next data element. Additionally, each memory element optionally further comprises a block size field indicating the variable size and/or a sequence number field indicating a sequence number of the corresponding data element. The buffer memory optionally comprises a largest sequence variable to store a sequence number of a data element in the buffer memory having a largest sequence number. The largest sequence variable is updated if a newly arrived data element has a sequence number that is larger than the largest sequence variable. A method is also provided for managing the disclosed buffer memories.

Methods and apparatus for linked-list circular buffer management

Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak; and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse.

Crest factor reduction (CFR) using asymmetrical pulses

A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KK. . . Kand U=U, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.

Mixed radix fast hadamard transform for communication systems

A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.

Multi-stage scheduler with processor resource and bandwidth resource allocation

A method for correcting at least one error in a data transmission over a packet-based communication network includes the steps of: generating a sequence of data packets for transmission over the packet-based communication network, the sequence of data packets being arranged into a plurality of packet frames, each of at least a subset of the packet frames including at least a primary data packet and a number of redundant data packets which is a function of a prescribed redundancy pattern, the subset of packet frames having a non-uniform distribution of redundant data packets therein; transmitting the sequence of data packets over the communication network; and recovering at least one missing data packet in the sequence of data packets using at least one corresponding redundant data packet in at least one subsequently received packet frame when the missing data packet is identified in a receiver of the sequence of data packets.

Method and apparatus for non-uniform redundancy packet error correction

Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

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Bridgewater, NJ, United States of America

Chengzhou Li