Qualcomm Incorporated

Chengzhi Pan

Joseph Patrick Burke

Christian Holenstein

Russell John Fagg

Wenqing Wu

Kendrick H Yuen

Raghu Sagar Madala

Abhishek Banerjee

The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Method and apparatus for facilitating power conservation via time-gating in a wireless communication system

Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics.

Spin torque transfer magnetic tunnel junction intelligent sensing

Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Passive switched-capacitor filters conforming to power constraint

A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies.

Discrete time receiver

Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter. In another example, the de-aggregator involves a decoder and the aggregator involves a precoder.

Radio channel aggregation and segmentation

Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

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San Diego, CA, United States of America

Chengzhi Pan