International Business Machines Corporation

Globalfoundries Inc.

Chengwen Pei

Geng Wang

Kangguo Cheng

Joseph Ervin

Ravi Mahendra Todi

Roger Allen Booth, Jr

Juntao Li

Zhengwen O Li

Ping-Chuan Wang

Jian Yu

Yanli Zhang

Paul Christian Parries

Jeffrey Bowman Johnson

Wai-Kin Li

Subramanian Srikanteswara Iyer

Gan Wang

Yan Zun Li

Pinping Sun

Xusheng Kevin Wu

Edward P Maciejewski

Kevin McStay

Ziyan Xu

Dechao Guo

Keith Kwong Hon Wong

Christian Lavoie

Chandrasekharan Kothandaraman

Kai D Feng

JunJun Li

Ahmet Serkan Ozcan

Byeong Yeol Kim

David Michael Fried

Filippos Papadatos

Robert Russell Robison

Herbert Lei Ho

Shreesh Narasimha

Werner A Rausch

Karen A Nummy

Jun Yuan

Oh-Jung Kwon

Yanfeng Wang

Xi Li

Randolph F Knarr

Junedong Lee

Maryjane Brodsky

Ali Khakifirooz

Huilong Zhu

Theodorus E Standaert

Robert J Gauthier, Jr

Zheng Xu

Toshiaki Kirihata

Michael Patrick Chudzik

Souvick Mitra

Babar Ali Khan

Jin Cai

Tom C Lee

Erdem Kaltalioglu

Christopher Stephen Putnam

Michael John Hargrove

Gregory Gower Freeman

Abhishek Dube

James Paul Di Sarro

Xiaojun Yu

Andrew Tae Kim

Kam Leung Lee

Gerd Pfeiffer

Brian W Messenger

Katsunori Onishi

Deepal Wehella-Gamage

Roger A Booth

Waikin Li

William R Tonti

Toshiharu Furukawa

Zhen Zhang

Brian Joseph Greene

Damon B Farmer

Pranita Kulkarni

Henry K Utomo

Paul S Chang

Zhibin Ren

David R Hanson

Dan Moy

Yang Liu

Christopher D Sheraw

Yue Ke

Richard Andre Wachnik

Frank Bin Yang

Chandrasekara Kothandaraman

Yue Tan

Anthony I-Chih Chou

Bidan Zhang

Naoyoshi Kusaba

Ravi K Dasaka

Yinxiao Yang

Rainer Loesing

Ning Zhan

Ahmed Nayaz Noemaun

Eric T Harley

A semiconductor device having transistors and anti-fuses integrated thereon includes a transistor region having a defect free monocrystalline semiconductor layer and a device channel for a transistor. The device also has an anti-fuse region including a defective semiconductor layer formed on an oxide of a portion of the surface of an epitaxial semiconductor layer over which the transistor is formed, the oxide having a thickness extending into the epitaxial semiconductor layer. It also has gate structures formed in the transistor region and in the anti-fuse region, where the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.

Anti-fuse with reduced programming voltage

A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Metal trench capacitor and improved isolation and methods of manufacture

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

Electrical and optical via connections on a same chip

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Wafer reinforcement to reduce wafer curvature

Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

Embedded metal-insulator-metal (MIM) decoupling capacitor in monolitic three-dimensional (3D) integrated circuit (IC) structure

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

Integrated circuit fabrication with boron etch-stop layer

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires

An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

Asymmetric FET

A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.

Fin structure in sublitho dimension for high performance CMOS application

Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line

High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

High density capacitor structure and method

Growing community of inventors

Danbury, CT, United States of America

Chengwen Pei