Marvell International Limited

Marvellworld Trade Ltd.

ChengKuo Huang

Xueshi Yang

Fei Sun

Siu-Hung Fred Au

Wei Xu

Siu-Hung Frederick Au

Tony Yoon

Lau Nguyen

Man Cheung

Bo Fu

Jinjin He

Sean Lee

Ka-Ming Keung

Sui-Hung Fred Au

Yaolong Gao

Grace Pao Yi Chen

Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.

Queuing of decoding tasks according to priority in NAND flash controller

A method for storing data on a storage device includes receiving data to be stored and a logical address for storing the data. A physical address is determined and the data to be stored is stored at the determined physical address. A table that associates logical addresses with physical addresses is examined to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses. Information representing the determined physical address is stored in the table, in association with the received logical address, as a function of the determined difference relationship. A data storage device includes controller circuitry and memory for storing a lookup table that associates logical addresses with physical addresses. The controller circuitry operates in accordance with the method.

Dynamic differential compression for storage device look-up table

A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Method and apparatus for detecting valid data using selective modification of cyclic redundancy codes

Embodiments of the present disclosure provide apparatuses and methods for determining a compacting arrangement to store logical addressable units, which include compressed data sectors, into hardware addressable units of a storage device. The compacting arrangement is based on compression information associated with the logical addressable units. A write module is used to write the compressed data sectors to the storage device according to the compacting arrangement.

Data compression and compacting for memory devices

A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.

Word-serial cyclic code encoder

Method and apparatus for determining whether a page in a flash memory system is in an erased state

Apparatus having corresponding methods and computer-readable media comprise an encoder configured to provide encoded data according to an error correction code; a flash memory interface configured to write the encoded data to a location in flash memory, and to read the encoded data from the location in the flash memory; a decoder configured to decode the encoded data read from the location in the flash memory, and to indicate a number of resulting decode errors; and a retirement module configured to retire the location responsive to a number of resulting decode errors reaching an error threshold T.

Method and apparatus for determining, based on an error correction code, one or more locations to store data in a flash memory

Erased page detection

A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words, respectively.

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Sunnyvale, CA, United States of America

ChengKuo Huang