Micron Technology Incorporated

Chengkuan Yin

Jiun-Horng Lai

Shinji Sato

Ronit Roneel Prakash

Yoshiaki Fukuzumi

Ching-Huang Lu

Pitamber Shukla

A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

Adaptive erase pulse width modulation based on erase suspend during erase pulse ramping period

A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

Sequential wordline erase verify schemes

A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

Growing community of inventors

Tokyo, Japan

Chengkuan Yin