Broadcom Corporation

Chengfuh Jeffrey Tang

Alexander Garland MacInnis

Xiaodong Xie

Greg Alan Kranawetter

James T Patterson

Sandeep Bhatia

Vivian T Hsiun

Francis Cheung

Yao-Hua Tseng

Darren Duane Neuman

Guang-Ting Shih

Alexander G Macinnis

Ramanujan K Valmiki

Steven (Yao-Hua) Tseng

Hsien-Chih Jim Tseng

Steven T Jaffe

Brian Francis Schoner

Rajesh Mamidwar

Patrick Y Law

Iue-Shuenn Chen

Aleksandr M Movshovich

Jason C Demas

Brad Albert Delanghe

David A Baer

Hoang Nhu

Ut Nguyen

Tracy C Denk

Sathish Kumar

Shawn Val Johnson

James Douglas Sweet

Jeffrey S Bauch

David Chao Hua Wu

Brad Grossman

Chuck Monahan

Dan Simon

Sang Van Tran

Lakshman Ramakrishnan

Thu T Nguyen

Ben Giese

Jeff Tingley

Keith LaRell Klingler

Jay Li

Steven Tseng

Guang Ting Shih

Kimming So

Sathish Kumar Radhakrishnan

Aniruddha Sane

Charles Thomas Monahan

Jiann-Tsuen Chen

Glenn Nissen

Wen Huang

Keith LaRell Klinger

Xiadong Xie

Nagesh Chatekar

Eric Tsang

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Graphics display system with unified memory architecture

Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

Graphics accelerator

Herein described is a method and system of vertically filtering a graphics image such that an enhanced image is provided to a display. Filtering of the graphics image may be accomplished by using one or more window descriptors. The method may be implemented by computing a weighted average of one or more pixel intensities. The system may comprise a memory, a processor, and a graphics engine. The graphics engine may comprise a graphics blender. The graphics blender may comprise one or more multipliers and one or more adders. The processor may execute software resident in the memory, such that the one or more window descriptors may be used to compute the weighted average.

Method and system for vertical filtering using window descriptors

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Television functionality on a chip

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Video and graphics system with video scaling

A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.

Video and graphics system with an integrated system bridge controller

A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Graphics display system with video scaler

A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Herein described is a method and system of displaying low resolution graphics onto a high resolution display. The low resolution graphics may be displayed using one or more displayable maps or surfaces, each of which is defined by way of one or more parameters. The display may comprise a monitor, television set, or set top box, capable of displaying at a particular resolution. In one or more representative embodiments, the various aspects of the invention permit scaling the low resolution graphics onto the high resolution display by way of using the one or more displayable maps or surfaces such that the graphics data is properly displayed on the higher resolution display.

Low resolution graphics mode support using window descriptors

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Graphics display system with anti-flutter filtering and vertical scaling feature

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.

Graphics display system with graphics window control mechanism

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Video, audio and graphics decode, composite and display system

A system and method, for reprogramming registers without having to reprogram unchanged registers. The registers are divided into groups based on common characteristics or functions. The values for the groups that differ from the current values are written into a linked list, which is then loaded into the appropriate registers. The linked list contains information indicating the groups of registers in the linked list.

Reprogramming of select registers in a linked list

Growing community of inventors

Satatoga, CA, United States of America

Chengfuh Jeffrey Tang