University of California

Chengcheng Wang

Dejan Markovic

Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Fine-grained power gating in FPGA interconnects

Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

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San Jose, CA, United States of America

Chengcheng Wang