Via Technologies, Inc.

Cheng-Yuan Wu

Chih-Hsien Weng

Chih Hsien Weng

Cheng-Shian Shiao

Chen-Hua Hsi

Chien-Cheng Chang

Wen-Hsu Huang

Stone Wei

A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module, making the memory send an interrupt request such that a new packet data can be read into the memory. This results in increased data transmission efficiency in the network interface circuit.

Method for increasing network transmission efficiency by increasing a data updating rate of a memory

Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage device stores first, second, third and fourth N-bit groups of a test pattern separately according to a loading signal and an address selection signal. The first multiplexing module is coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first, second, third and fourth N-bit groups which will be received and executed by the first digital logic circuit module to parallel generate first, second and third M-bit groups. The selection device is coupled to the first digital logic circuit module for sequentially selecting one of the first, second and third M-bit groups to output a first test result according to the address selection signal.

Systems and methods for chip testing

Method and related circuit for increasing network transmission efficiency by increasing a data updating rate of a memory

A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.

Method and device for coordinating packet transmission order

A method of configuring a computer system capable of being woken up on a LAN A core power is actuated for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, a PCI clock signal is retrieved in the fixed interval and then an Ethernet ID is loaded using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. As a result, use of an oscillator in conventional methods can be reduced, and the computer system can be configured to be capable of being woken-up on LAN, without requiring the start-up procedure, so that the computer system may be awoken on the LAN even after an abnormal shutdown.

Method of configuring a computer system capable of being woken up on LAN

A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p&#x2212;q)th detected points but a second level at the (p+1)th detected point.

Method and device for verifying frequency of clock signal

A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

Growing community of inventors

Taipei, Taiwan

Cheng-Yuan Wu