Micron Technology Incorporated

Cheng Yuan Wu

Ying Yu Tai

Samir Mittal

Jiangli Zhu

Zhengang Chen

Ning Chen

Wei Wang

Gurpreet Anand

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Memory systems having controllers embedded in packages of integrated circuit memory

A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Memory sub-system including an in package sequencer separate from a controller

A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

Controller with distributed sequencer components

A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller

A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.

Write buffer management

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component.

A read operation to retrieve data from memory component and that bypasses a prior search for the data at a buffer in a read data path associated with the read operation can be performed. Responsive to performing the read operation that bypasses the prior search for the data at the buffer, the data is returned to a host system.

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Fremont, CA, United States of America

Cheng Yuan Wu