Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Yuan Tsai

Hsing-Lien Lin

Chia-Shiung Tsai

Hai-Dang Trinh

Cheng-Hsien Chou

Yao-Wen Chang

Sheng-Chau Chen

Hsun-Chung Kuang

Sheng-Chan Li

Yeur-Luen Tu

Kuo-Ming Wu

Han-Chin Chiu

Chin-Wei Liang

Bi-Shen Lee

Chih-Hui Huang

Fa-Shen Jiang

Jian-Shiou Huang

Neng-Kuo Chen

Ming-Che Lee

Kai-Wen Cheng

Wen-Ting Chu

Chii-Ming M Wu

Ru-Liang Lee

Kuo-Hwa Tzeng

Chen-Fa Lu

Cheng-Tai Hsiao

Hau-Yi Hsiao

Trinh Hai Dang

Chih-Ming Chen

Chih-Yu Lai

Yen-Chang Chu

Yi Yang Wei

Cheng-Ta Wu

Chi-Ming Chen

Fu-Wei Yao

Chun-Han Tsao

I-Nan Chen

Tzu-Chung Tsai

Kong-Beng Thei

Chung-Yi Yu

Chin-Chieh Yang

Lan-Lin Chao

Keng-Yu Chou

Szu-Yu Wang

Yung-Lung Lin

Min-Ying Tsai

Chih-Lung Lin

Han-Yu Chen

Harry-Hak-Lay Chuang

Chern-Yow Hsu

Yu-Wen Liao

Xiaomeng Chen

Chung-Long Chang

Shing-Chyang Pan

Yen-Ting Chiang

Shih-Pei Chou

Tsun-Kai Tsao

Kuei-Hung Shen

Ching-Chung Hsu

Albert Zhong

Chih-Wei Lin

Yu-Jen Wang

You-Hua Chou

Ping-Yin Liu

Hsia-Wei Chen

Yi-Huan Chen

Chia-Hua Lin

Kuan-Liang Liu

Chih-Hsiang Chang

Tzu-Yu Lin

Yao-Chung Chang

Eugene I-Chun Chen

Yu-Syuan Lin

Sheng-De Liu

Bang-Tai Tang

Tzu-Hsiang Chen

Cheng-Chen Calvin Hsueh

Dun-Nian Yaung

Jen-Cheng Liu

Chun-Wen Cheng

Chao-Hsiung Wang

Yen-Liang Lin

King-Yuen Wong

Wen-Chuan Chiang

Ya-Chen Kao

Chun-Jung Lin

Ching I Li

Kuo-Liang Lu

Jeffrey Junhao Xu

Ping-Tzu Chen

Ming-Wei Tsai

Huey-Chi Chu

Min-Chang Ching

Chun-Chi Chen

Guanyu Luo

Zhi-Yang Wang

Jui-Lin Chu

Wen-Yuan Hsieh

Ming-Te Liu

Wei-Min Tseng

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

Deep trench isolation structure and methods for fabrication thereof

A semiconductor device structure is provided. The structure includes a substrate and a data storage element over the substrate. The structure also includes a protective element extending into the data storage element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.

Memory device structure with data storage element

Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Resistive memory cell with switching layer comprising one or more dopants

A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

FeRAM with laminated ferroelectric film and method forming same

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Interface film to mitigate size effect of memory device

A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.

Tunable plasma exclusion zone in semiconductor fabrication

A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Capacitor structure and method of making the same

The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

RRAM device with improved performance

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Techniques for wafer stack processing

Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Conductive structure connection with interconnect structure

The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate

Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

High reflectance isolation structure to increase image sensor performance

A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

Method and system for adjusting the gap between a wafer and a top plate in a thin-film deposition process

Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Diffusion barrier layer in programmable metallization cell

In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Cleaning chamber for metal oxide removal

Growing community of inventors

Chu-Pei, Taiwan

Cheng-Yuan Tsai