Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Cheng Yuan Hsiao

Ke-Wei Su

Min-Chie Jeng

Chung-Kai Lin

Yi-Shun Huang

Juan Yi Chen

Katherine H Chiang

Ke-Ying Su

Chia-Yi Chen

Lester Chang

Te-Yu Liu

Ya-Chin Liang

Chang-Yu Huang

Jaw-Kang Her

Wai-Kit Lee

Sung Kao Liu

Jia-Lin Lo

Feng-Ling Hsiao

Chewn-Pu Jou

Yi-Chun Chen

Sally Liu

Li-Chung Hsu

Cheng-Tse Tang

Ping-Hung Yuh

Chi Wu

Ting-Sheng Huang

Wen-Cheng Huang

Yi Ting Chien

Chien Min Chen

Chih Yu Hsu

Juan-Yi Chen

Wei Hung Chuang

Chen-Ming Tsai

Chia-Ju Yu

The present disclosure relates to optical waveguide termination devices. In some embodiments, an optical waveguide termination device is coupled to an end of an optical waveguide. The optical waveguide termination device is a tapered structure. In various embodiments, an optical absorption rate of the tapered structure is increased to enhance a termination efficiency. The optical absorption is increased by highly-doped material, multi-layer structure, different cladding, and periodic structure. The enhancement of the termination efficiency benefits size reduction of the tapered structure.

Optical waveguide termination

The present application discloses an adapter for data transmission between a first communication device and a second communication device, in which the first communication device reads data in the second communication device, and the data includes a plurality of data segments, wherein a size of each data segment is the maximum transmission unit of the second communication device. The adapter includes a buffer and a plurality of counters. The buffer stores the data transmitted by the second communication device temporarily. The plurality of counters are initially set to zero. Each counter corresponds to each data segment and indicates a size of partial data of each data segment that has been stored. The adapter transmits the partial data to the first communication device, when each counter indicates that the size of the partial data reaches a predetermined transmission unit but does not reach the maximum transmission unit.

Adapter and data transmission method under limited memory

A circuit includes: a first interface circuit supporting multiple first interface operating modes respectively corresponding to different versions of a first data transmission protocol; a second interface circuit supporting multiple second interface operating modes respectively corresponding to different versions of a second data transmission protocol; a control circuit configured to operably instruct the first interface circuit to operate in a first target operating mode selected from the multiple first interface operating modes, and configured to operably instruct the second interface circuit to operate in a second target operating mode selected from the multiple second interface operating modes; wherein a difference between a nominal data rate of the first target operating mode and a nominal data rate of the second target operating mode is less than a predetermined threshold.

Interface bridge circuit capable of reducing heat generation

An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Method and system for integrated circuit design with on-chip variation and spatial correlation

A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Method for establishing aging model of device and analyzing aging state of device with aging model

A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

Simulation scheme including self heating effect

A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Method for analyzing interconnect process variation

A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.

Method of designing circuit layout and system for implementing the same

The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.

Circuit device reliability simulation system

A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.

Constructing mapping between model parameters and electrical parameters

A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.

Unified model for process variations in integrated circuits

Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.

Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof

A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.

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Hsinchu, Taiwan

Cheng Yuan Hsiao