Advanced Semiconductor Engineering, Inc.

Cheng Yuan Chen

Chun Chen Chen

Yuanhao Yu

Jiming Li

Chih-Cheng Lee

Chi-Tsung Chiu

Cheng-Lin Ho

Hui-Ying Hsieh

Chien-Wen Tu

Kuo-Hua Chen

Hui Hua Lee

A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.

Semiconductor device package, electronic assembly and method for manufacturing the same

A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.

Semiconductor packages and methods of manufacturing the same

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A Sparameter of the connector is less than −20 dB.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than &#x2212;20 dB.

A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

Semiconductor package structure and method for manufacturing the same

A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.

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Kaohsiung, Taiwan

Cheng Yuan Chen