Lextar Electronics Corporation

Mediatek Corporation

Tsinghua University

Realtek Semiconductor Inc.

Novatek Microelectronics Corp.

Cheng-Yu Tsai

Jian-Chin Liang

Jo-Hsiang Chen

Lung-Kuan Lai

Hsin-Lun Su

Ting-Kai Chen

Hui-Ru Wu

Yuan Yuan

Peng Yang

Jianwei Zhang

Han-Chieh Hsieh

Jya-Wei Cheng

Hui-Yuan Yu

Yu-Cheng Lo

Yu-Hung Su

Zhi Zheng

Kuan-Lin Chen

Jung-Chieh Cheng

Lee-Wei Yang

Nien-En Wu

Yen-Chen Chen

Shih-Jung Hsu

Hong-Chun Li

Jun Hu

Shu-Yu Chang

Apparatus and methods are provided for determining AR filter coefficient and numbers of synchronization. In one novel aspect, the AR filter coefficient and times of synchronization are determined based on the temperatures of the oscillator. In one embodiment, the UE determines a temperature drift rate by collecting sets of temperatures before and after the UE in the sleep mode of the CDRX, generates one or more threshold look-up tables and performs an optimization selection based on the temperature drift rate and the one or more threshold of look-up tables, wherein the optimization selection comprising selecting an alpha coefficient and a number of subframes for synchronization. In another embodiment, the optimization selection is further determined based on a subcarrier spacing, and a channel type of being a static channel type and a fading channel type. The UE further performs an on-the-fly oscillator S-curve calibration based on the set of temperatures.

Methods and apparatus for determining ar filter coefficient and times of synchronization

A pixel array package structure includes: a substrate; a pixel array disposed on the substrate, in which the pixel array includes a plurality of light emitting diode chips, and the light emitting diode chips include at least one red diode chip, at least one green diode chip, at least one blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two adjacent of the light emitting diode chips; a light-absorbing layer disposed on the reflective layer and surrounding the pixel array; and a light-transmitting layer disposed on the pixel array, the reflective layer, and the light-absorbing layer, in which the light-transmitting layer has an upper surface and a lower surface opposite thereto, and the lower surface is in contact with the pixel array, and the upper surface has a roughness of 0.005 mm to 0.1 mm.

Pixel array package structure and display panel

A timing control circuit and an operating method thereof are provided. The timing control circuit includes a first clock generating circuit, a second clock generating circuit and a control timing generating circuit. The control timing generating circuit is coupled to the first clock generating circuit to receive a first clock signal. The control timing generating circuit is coupled to the second clock generating circuit to receive a second clock signal. The control timing generating circuit starts timing from a first reference time point according to the first clock signal for determining a second reference time point. The control timing generating circuit starts timing from the second reference time point according to the second clock signal for determining a time point of a trailing edge of a current line pulse of a scan reference signal, wherein the current line pulse corresponds to a current scan line of a display panel.

Timing control circuit and operating method thereof

Disclosed is an IC layout design method capable of improving a result of an integrated circuit (IC) layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to an initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining an updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.

IC layout design method

A display device includes a substrate, a light-emitting member, and an anti-reflective glass layer. The light-emitting member is on the substrate. The anti-reflective glass layer is over the light-emitting member, and the anti-reflective glass layer has a transmittance of 40-95%. The anti-reflective glass layer includes a glass layer and a light-absorbing layer. The glass layer has a rough top surface and a haze of 70-80%. The light-absorbing layer is on the rough top surface of glass layer.

Display device

The present invention provides an evaluating system and the use thereof for the efficacy of antimicrobial peptide, which includes the following steps: (a) constructing a peptide by a first input unit, and load the peptide into an aqueous solution for a first time for equilibration; (b) constructing a lipid bilayer by a second input unit, and load the lipid bilayer into an aqueous solution for a second time for equilibration; (c) Using a first processing unit, simulations are carried out for an aqueous system containing an equilibrated peptide from the first input unit and the equilibrated lipid bilayer from the second input unit; (d) calculating the partition free energy of the peptide by a second processing unit; (e) outputting the prediction by an output unit, wherein the output unit is connected with the first processing unit and the second processing unit.

In silico design of peptides equilibrated in a lipid bilayer with partition free energies indicating probability of antimicrobial activity

Growing community of inventors

Hsinchu, Taiwan

Cheng-Yu Tsai