Realtek Semiconductor Inc.

Novatek Microelectronics Corp.

Cheng-Yu Liu

Tsung-Ming Chen

Yi-Jang Wu

Chia-Jung Chang

Shawn Min

Chiao-Wei Hsiao

Chun-I Kuo

Chun-Ta Ho

Yu-An Chang

Chieh-Yuan Hsu

Chieh-Shiung Chang

A voltage meter includes a sampler, a gain circuit, an accumulator and a feedback circuit. The sampler samples an input signal to generate a series of first signals and a series of second signals. The gain circuit, coupled to the sampler, modifies at least one of the series of first signals and the series of second signals, to generate a series of modified first signals and a series of modified second signals. The accumulator, coupled to the gain circuit, accumulates an operational result of the series of modified first signals and the series of modified second signals, to generate an accumulation result. The feedback circuit, coupled between the accumulator and the sampler, sends a feedback signal back to the sampler according to the accumulation result.

Voltage meter for measuring signal inside integrated circuit

The present invention discloses a signal output circuit applying bandwidth broadening mechanism for an image signal transmission apparatus that includes a first driving circuit and a second driving circuit. The first driving circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a first output signal, in which a zero point and two poles of a frequency response of the first driving circuit are determined by circuit parameters thereof. The second driving circuit is configured to receive and amplify the first output signal to generate a second output signal for an image receiving apparatus.

Image signal transmission apparatus and signal output circuit applying bandwidth broadening mechanism thereof

A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.

Control chip supporting consumer electronics control protocol and high voltage tolerant output circuit thereof

Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Open loop fractional frequency divider

A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.

Growing community of inventors

Hsinchu, Taiwan

Cheng-Yu Liu