Taiwan Semiconductor Manufacturing Comp. Ltd.

Assier Conductor Manufacturing Company, Ltd.

Cheng-Yu Lin

Hui-Zhong Zhuang

Jerry Chang Jui Kao

Yung-Chen Chien

Chih-Liang Chen

Sheng-Hsiung Chen

Huang-Yu Chen

Wei-Ren Chen

Jia-Hong Gao

Lee-Chung Lu

Chung-Hsing Wang

Po-Hsiang Huang

Kuo-Nan Yang

Jung-Chan Yang

Fong-Yuan Chang

Pochun Wang

Xiangdong Chen

Yi-Lin Fan

An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.

Integrated circuit device, method and system

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Layout design for header cell in 3D integrated circuits

An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

Integrated circuit device and method

A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Semiconductor device and method of manufacturing the same

An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

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Hsinchu, Taiwan

Cheng-Yu Lin