Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Yu Kuo

Ching-Hua Hsieh

Yi-Yang Lei

Chen-Hua Douglas Yu

Chung-Shi Liu

Wei-Jie Huang

Alexander Kalnitsky

Chin-Yu Ku

Kuo-Chio Liu

Ching-Pin Yuan

Kuo-Pin Chang

Kai-Di Wu

Sheng-Pin Yang

De-Dui Liao

Hsi-Ching Wang

Tsung Lung Huang

Isaac Huang

Yu-Ching Lo

Kei-Wei Chen

Chih Hung Chen

William Weilun Hong

Te-Chien Hou

Yu-Ting Yen

Wen-Chih Lin

A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.

Workpiece chuck, workpiece handling apparatus, manufacturing method of semiconductor package

A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

Lamination process, and manufacturing method of semiconductor package using a chuck

A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

CMP system and method of use

Chuck, lamination process, and manufacturing method of semiconductor package using the same

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Package structure and method of fabricating the same

A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Method of manufacturing semiconductor structure

A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.

A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.

A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.

Semiconductor structure and manufacturing method thereof

Growing community of inventors

Kaohsiung, Taiwan

Cheng-Yu Kuo