Other

Thomson Multimedia S.a.

Panasonic Technologies, Inc.

Centillium Communications, Inc.

Mitsubishi Electric Information Technology Center America, Inc (ita)

Cheng-Youn Lu

Charles A Reed, Jr

Randall Bret Perlow

Jay Bao

Tommy C Poon

Judith Wang

Robert S Burroughs

A method for detecting an input signal at a transceiver of a communication system is disclosed, and includes compensating for timing misalignment between when the receipt of the input signal was indicated and when the input signal actually arrived. A signal detector for detecting an input signal and adapted to compensate for timing misalignment is also disclosed.

Two-dimensional signal detector with dynamic timing phase compensation

Method and apparatus for determining the correct set of samples to retain in applying a decimation process. The present method provides an automatic approach to determine the timing phase of the desired samples to decimate the oversampled input signal (data sequence), thereby producing the underlying data signal.

Method and apparatus for decimating an oversampled signal

An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.

Data receiver having variable rate symbol timing recovery with

A sparse digital adaptive equalizer including forward and feedback Finite Impulse Response (FIR) filters exhibits improved Least Mean Square operation. A switch assigns one of several multipliers of each filter to any one of the tap locations of that filter. Each multiplier is initially assigned to a preselected tap location with a predetermined weighting coefficient. After completing successive time cycles having a duration equal to a given number of data sample periods, for each filter there is determined (a) a first group of coefficients associated with multipliers then assigned to non-zero value tap locations, and (b) a second group of coefficients associated with multipliers then assigned to zero valued locations. Multipliers associated with first group coefficients during a just-completed time cycle retain their tap locations during the next time cycle. Multipliers associated with second group coefficients during a just-completed time cycle are reassigned to new tap locations for use during the next time cycle.

Sparse equalization filter adaptive in two dimensions

A quadrature demodulator for demodulating an input signal which includes respective data signals modulating in-phase and quadrature carriers. The demodulator includes a voltage controlled oscillator responsive to a control signal for generating an oscillatory signal. A demodulator, coupled to receive the oscillatory signal from the voltage controlled oscillator and the input signal, provides the in-phase and quadrature components of the input signal. Phase comparison circuitry, responsive to the in-phase and quadrature components of the input signal generates a phase error signal. The phase error signal represents the difference, in phase and magnitude, between a vector defined by the in-phase and quadrature components of the input signal and reference vectors. Filter circuitry, responsive to the phase error signal, generates a control signal for the voltage controlled oscillator. Phase error correction circuitry selectively applies the error signal to the filter circuitry when the magnitude of a vector defined by the in-phase and quadrature components of the input signal exceeds a first threshold. Another embodiment provides the phase error signal to the filter circuitry when the magnitude of a vector defined by the in-phase and quadrature components of the input signal either exceeds a first threshold or is less than a second threshold.

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Cresskill, NJ, United States of America

Cheng-Youn Lu