Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Yi Hong

Shin-Puu Jeng

Shuo-Mao Chen

Feng-Cheng Hsu

Po-Yao Lin

Shu-Shen Yeh

Mill-Jer Wang

Chih-Hsien Lin

Chen-Hua Lin

Chao-Hsiang Yang

Kuang-Chun Lee

Dai-Jang Chen

Hsiang-Tai Lu

Ming-Chih Yew

Wen-Yi Lin

Kuo-Chuan Liu

Hsiang-tai Lu

A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Semiconductor structure and manufacturing method thereof

A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

Method of forming semiconductor device package

A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.

Method of forming semicondcutor device package

A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.

Semiconductor device package and method of forming semiconductor device package

Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.

Method of forming encapsulated semiconductor device package

Semiconductor device package and method

Growing community of inventors

Hsinchu, Taiwan

Cheng-Yi Hong