Pmc-sierra, Inc.

Silicon Motion, Inc.

Pmc-sierra Us, Inc.

Microsemi Solutions (us), Inc.

Microsemi Storage Solutions, Inc.

Cheng Yi

Heng Liao

David Joseph Clinton

Paul Chong

Kaihong Wang

Sheng-I Hsu

Janardan Prasad

Praveen Alexander

Calvin Leung

Raymond Lam

I-Ling Tseng

Tao Zhong

Gary Nichols

A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

Method and apparatus for performing data access performance shaping of memory device

A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

Memory and apparatus for performing access control with aid of multi-phase memory-mapped queue

SAS expanders are commonly used within a SAS network topology to allow multiple disk drives (targets) to connect to multiple host devices (initiators). A connection between an initiator and a target is setup inside an expander on the pathway between the initiator and the target. A source device sends a connection request message called an open address frame using in-band signaling. The expander processes the open address frame and forwards an modified open address frame to the next expander in the path or to the final destination device.

Method and apparatus for SAS open address frame processing in SAS expanders

A method and apparatus for handling SGLs for out of order systems is disclosed. The method involves generating multiple Child IOs from an original IO, each Child IO being at the granularity of a storage side memory; generating separate SG lists for each Child IO; and processing each Child IO independently of other Child IOs and in order with each Child IO for data transfer. As each Child IO is generated at the granularity of the storage side memory, the Child IOs can be processed independently of each other and in-order within each Child IO. Thus, an out-of order IO transfer is transformed into an in-order IO transfer.

Apparatus and method for scatter gather list handling for an out of order system

A method of chaining a plurality of engines for a system on chip (SOC) controller device and a SOC controller device are disclosed herein. The method comprises: generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller; passing the super-descriptor from the initiator to a first engine of the plurality of engines; and executing a portion of the super-descriptor at each of the plurality of engines in series without the intervention of the initiator.

System and method for multiengine operation with super descriptor in SAS/SATA controller wherein portion of super-descriptor is executed without intervention of initiator

A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

System and method for scatter gather cache processing

A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.

Serial tunneling protocol (STP) flow control in SAS expanders without SATA link state machine

The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

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Vancouver, Canada

Cheng Yi