Chartered Semiconductor Manufacturing Ltd (corporation)

New Silicon Corporation Pte Ltd

Cheng Yeow Ng

Shao-fu Sanford Chu

Kiat Seng Yeo

Choon-Beng Sia

Wang Ling Goh

Kok Wai Chew

Eugene A Fitzgerald

Alex See

Randall Cher Liang Cha

Tae Jong Lee

Chua Chee Tee

Kenneth Eng Kian Lee

Toe Naing Swe

Fayyaz Moiz Singaporewala

A method of fabricating a semiconductor device () is described. According to a described embodiment, the method comprises: (i) forming a III-V semiconductor material layer () comprising a substrate layer () and a device layer () attached to the substrate layer (); and (ii) forming an electrically conductive interlayer () to the device layer () prior to bonding the electrically conductive interlayer () to a partially processed CMOS device layer () having at least one transistor ().

Method for fabricating a semiconductor device including integrating III-V device and CMOS device, and the semiconductor device thereof

A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

Method of manufacturing 3-D spiral stacked inductor on semiconductor material

A 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

3-D spiral stacked inductor on semiconductor material

A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.

Parallel spiral stacked inductor on semiconductor material

A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer. The capacitor dielectric layer and the first metal layer are patterned wherein the patterned first metal layer forms a bottom metal electrode and wherein the spacers protect the top metal layer from etching during the patterning. The photoresist mask is removed, completing fabrication of a metal-insulator-metal capacitor.

Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors

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Singapore, Singapore

Cheng Yeow Ng