United Microelectronics Corp.

Andes Technology Corporation

Cheng-Yen Huang

Chih-Ming Shen

The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.

Configurable memory system and memory managing method thereof

A sequential memory access circuit for access to various memory units is provided. The sequential memory access circuit is coupled between an external system and at least two memory units including a RAM unit and a ROM unit. The sequential memory access circuit includes a common data pointer circuit, responsive to a reset signal, a write request signal, and a read request signal from said external system, for generating accordingly a RAM enable signal, a ROM enable signal, and a counter signal, for control of the access to the RAM unit and the ROM unit. Further, a length register is used to generate a bound control signal to said common data pointer circuit in response to the write request signal and the counter signal. A sequential access dedicated comparator is used to provide the controls for the access to the two memory units. The structure of the sequential memory access circuit allows for a small circuit layout area and a reduced delay time.

Sequential memory accessing circuit and method of addressing two memory

A computer address translation method and system applicable in CPUs for translating an effective address and a selector address into a physical address under the control of an invalidity signal through a translation lookaside buffer having a stored first address and a stored second address. An effective address and a selector address are simultaneously input to the translation lookaside buffer such that address translation and linear address production are parallel processed, thereby effectively speeding up the address translation process.

Growing community of inventors

Hsinchu, Taiwan

Cheng-Yen Huang