Realtek Semiconductor Inc.

Cheng-Yan Wen

Ying-Yen Chen

Jih-Nung Lee

Wen-Hsuan Hsu

Chia-Tso Chao

The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N&#xd7;M records of quiescent DC current (IDDQ) data; generating N reference values according to the N&#xd7;M records, in which each of the N reference values is generated according to M record(s) of the N&#xd7;M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N&#xd7;M records by the reference order so as to obtain reordered N&#xd7;M records; generating an IDDQ range according to the reordered N&#xd7;M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

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Taipei, Taiwan

Cheng-Yan Wen