United Microelectronics Corp.

Cheng-Wen Fan

Chih-Yu Tseng

Kun-Szu Tseng

Hua-Chou Tseng

Victor-Chiang Liang

Victor Chiang Liang

Che-Hua Hsu

Chien-Ting Lin

Chun-Yao Ko

Chien-Kuo Yang

Yu-Ho Chiang

Chih-Yuh Tzeng

Jiunn-Ren Hwang

Tsun-Lai Hsu

Kai-Ling Chiu

Chun-Yi Lin

Chih-Chiang Liu

Chih-Chen Hsueh

Chien-Chou Hung

Hsin-Kai Chiang

Chia-Hung Chin

Ellis Lin

Chia-Hong Chin

Cheng-Choug Hung

Kay Ming Lee

A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.

Metal gate transistor with resistor

An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.

Method for fabricating metal gate transistor and polysilicon resistor

A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.

Semiconductor device and method of forming the same

A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Metal gate transistor and resistor and method for fabricating the same

An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.

Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Method for reducing capacitance variation between capacitors

Structure of capacitor set

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.

Semiconductor structure and method of forming the same

The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the emitter and on the first extrinsic base region. The first extrinsic base region is adjacent the intrinsic base region and the second extrinsic base region is adjacent the first extrinsic base region on the substrate, wherein a dopant concentration of the second extrinsic base region is higher than a dopant concentration of the first extrinsic base region.

Heterojunction bipolar transistor

An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.

Method of fabricating inductor and structure formed therefrom

A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the base-emitter. Next, a second poly silicon layer, which has a dopant concentration range within 1E19 to 1E21 (atom/cc), is deposited by SEG method. It not only reduces the resistance of the SiGe base layer, but also avoids the annealing that may influence the performance of the device.

Formation method of SiGe HBT

A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected so as to prevent a plasma micro-loading effect.

Method of correcting a mask layout

A fabrication method for heterojunction bipolar transistor is disclosed. The method uses ISSG oxide instead of conventional PECVD oxide so that the base/emitter interface damage can be reduced. Moreover, the invention replaces the conventional emitter-window/space mask with an emitter-window reverse-tone mask/line mask to minimize the critical dimension of emitter window. Furthermore, the invention also utilizes a two-steps extrinsic base implantation to form two extrinsic bases with different dopant concentrations so that the base resistance can be reduced.

Growing community of inventors

Tainan County, Taiwan

Cheng-Wen Fan