Vanguard International Semiconductor Corporation

Delta Electronics, Inc.

Cheng-Wei Chou

Hsin-Chih Lin

Shin-Cheng Lin

Yu-Chieh Chou

Yung-Fong Lin

Cheng-Tao Chou

Chia-Lin Chen

Xin-Hung Lin

Kwang-Ming Lin

Chen-Wei Ku

Chang-Xiang Hung

Szu-Yao Chang

Ting-En Hsieh

Hsiu-Ming Chen

Yung-Fung Lin

Chi-Fu Lee

Yi-Han Huang

Shu-Wen Chang

Hsiu-Ming Wu

A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Semiconductor structure

A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.

Semiconductor structure and method of forming the same

A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.

Semiconductor structure with gate metal layer

A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

High electron mobility transistor and method for forming the same

A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.

Semiconductor device and method of forming the same

A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.

Semiconductor structures and methods of forming the same

A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.

Semiconductor structure and method for forming the same

A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.

Semiconductor devices and methods for forming the same

A mounting assembly and an inverter assembly using the same are disclosed. The mounting assembly includes a waterproof component and a fixing component. The waterproof component includes a first side facing the inverter, a second side facing the wall surface, an opening and a gasket set. The opening runs through the first side and the second side. The gasket set is disposed around the opening. The gasket set abuts against the wall surface and the inverter. The inverter is electrically connected with a wire running through the opening. The fixing component is disposed on the wall surface and connected to the waterproof component. The fixing component includes a third surface facing the inverter, a fourth surface facing the wall surface, and a first engaging element. The first engaging element engages with a second engaging element of the inverter to mount the inverter on the wall surface.

Mounting assembly and inverter assembly using same

A method for manufacturing a semiconductor device structure is provided. The method includes providing a base substrate and forming a buffer layer on the base substrate. The method also includes forming a patterned silicon layer on the buffer layer. The patterned silicon layer has an opening to expose a portion of the buffer layer. The method further includes epitaxially growing a patterned channel layer and a patterned barrier layer on a top surface of the patterned silicon layer sequentially. In addition, the method includes forming a gate electrode on the patterned barrier layer.

Semiconductor device structures and methods for manufacturing the same

A semiconductor device includes a substrate, a flowable dielectric material and a GaN-based semiconductor layer. The substrate has a pit exposed from an upper surface of the substrate, the flowable dielectric material fully fills the pit, and the GaN-based semiconductor layer is disposed over the substrate and the flowable dielectric material.

Growing community of inventors

Taoyuan, Taiwan

Cheng-Wei Chou