International Business Machines Corporation

Globalfoundries Inc.

Macronix International Co., Ltd.

King Abdulaziz City for Science and Technology

Cheng-Wei Cheng

Kuen-Ting Shiu

Devendra K Sadana

Effendi Leobandung

Ning Li

Yanning Sun

Amlan Majumdar

Stephen W Bedell

Sanghoon Lee

Ko-Tao Lee

Tak H Ning

Jeehwan Kim

Renee Tong Mo

Pranita Kerber

Shu-Jen Han

John Albrecht Ott

Can Bayram

Jeng-Bang Yau

Brent A Wacaser

Katherine Lynn Saenger

Jack Oon Chu

Edward William Kiewra

Masaharu Kobayashi

Uzma B Rana

Norma Edith Sosa Cortes

Kevin K Chan

Tze-Chiang Chen

Robert L Bruce

Young-Hee Kim

Keith E Fogel

Anirban Basu

Kunal Mukherjee

Alexander Reznicek

Ruilong Xie

Pouya Hashemi

Ghavam G Shahidi

Bahman Hekmatshoartabari

Guy M Cohen

Davood Shahrjerdi

Heng Wu

Wilfried Haensch

Hiroyuki Miyazoe

Frank Robert Libsch

David Lee Rath

Matthew Joseph BrightSky

Leathen Shi

Nanbo Gong

Huai-Yu Cheng

Hongsik Park

I-Ting Kuo

Ibrahim A Alhomoudi

Hsiang-Lan Lung

Martin Michael Frank

Seyoung Kim

Tayfun Gokmen

Dae-Gyu Park

Augustin J Hong

Wanki Kim

HsinYu Tsai

Szu-Lin Cheng

Pierce I-Jen Chuang

Asit Kumar Ray

Norma Edith Sosa

Ryan M Martin

Gloria Wing Yun Fraczak

Matthew Joseph Brightsky

Keun-Ting Shiu

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

Suppression of void-formation of PCM materials

An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

Phase-change memory cell with mixed-material switchable region

A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Direct growth of lateral III-V bipolar transistor on silicon substrate

A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.

Mitigating moisture driven degradation of silicon doped chalcogenides

Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.

PCM cell with resistance drift correction

Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.

Reactivation of a deposited metal liner

An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.

Suppressing oxidation of silicon germanium selenium arsenide material

A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.

III-V transistor device with self-aligned doped bottom barrier

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

III-V CMOS co-integration

A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.

Gate-all-around field effect transistor using template-assisted-slective-epitaxy

A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.

Multi-state transistor devices with multiple threshold voltage channels

A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.

III-V photonic integrated circuits on silicon substrate

A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

Growing community of inventors

White Plains, NY, United States of America

Cheng-Wei Cheng