Industrial Technology Research Institute

Hestia Power Inc.

Fast Sic Semiconductor Incorporated

Eternal Chemical Co., Ltd.

Shanghai Hestia Power Inc.

Cheng-Tyng Yen

Chien-Chung Hung

Chwan-Ying Lee

Young-Shying Chen

Fu-Jen Hsu

Hsiang-Ting Hung

Lurng-Shehng Lee

Yao-Feng Huang

Wei-Chuan Chen

Meng-Yen Chou

Chung-Jen Wu

Ding-Yeong Wang

Shu-Wan Lu

Min-Chi Wang

Chung-Hung Chang

Chin-Chang Chuang

Hsin-Wei Huang

Chin-Min An

Chung-Hao Wu

Wen-Chang Chen

Yu-Wen Wang

Kuo-Huang Hsieh

Chiao-Shun Chuang

Yung-Hung Wang

Kuo-Ting Chu

Cheng-Chin Huang

Kai-Yu Chen

Kuan-Wei Chu

A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.

Silicon carbide semiconductor device

Embodiments relate to a cascode diode circuit. The cascode diode circuit comprises a normally on transistor, a low voltage diode and a high voltage diode. The normally on transistor has a gate, a drain, and a source. The low voltage diode has a cathode connected to the source of the normally on transistor and an anode connected to the gate of the normally on transistor. The high voltage diode has a cathode connected to a node between the normally on transistor and the low voltage diode, and an anode connected the drain of the normally on transistor.

Cascode diode circuit

A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (W) which is satisfied the following formula:+2×+2×Lrepresents a channel length of channel regions, Wrepresents a minimum width of JFET regions, and Lrepresents a minimum overlapping length between the gate electrode and the second doped region.

Silicon carbide MOS-gated semiconductor device

A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Power transistor module and controlling method thereof

The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

Silicon carbide semiconductor device integrating clamper circuit for clamping voltage

A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing.

A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or fed back from the power transistor device; wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.

A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.

Semiconductor power device

A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.

An intelligent power component module operable to be driven by a negative gate voltage integrates a wide bandgap semiconductor power unit, an adjustment unit and a driving unit so as to adjust a voltage level of the driving unit by the adjustment unit. Accordingly, the wide bandgap semiconductor power unit, in a driven state, comprises a driving voltage level alternating between a positive and a negative voltage.

Intelligent power module operable to be driven by negative gate voltage

A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.

Silicon carbide semiconductor element and manufacturing method thereof

A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.

Wide bandgap semiconductor device with adjustable voltage level

A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.

Growing community of inventors

Hsinchu, Taiwan

Cheng-Tyng Yen