Ememory Technology Inc.

Cheng-Te Yang

Wu-Chang Chang

Tsung-Mu Lai

Chen-Hao Po

Hung-Hsiang Wang

Chih-Hsin Chen

Cheng-Heng Chung

A memory device includes a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N/2+1) bit lines, (N/2) source lines and reference cells, N being a positive even integer. Each row of reference cells includes a (2n&#x2212;1)th reference cell and a (2n)th reference cell. The (2n&#x2212;1)th reference cell includes a first terminal coupled to an nth bit line, and a second terminal coupled to an nth source line, n being a positive integer less than N/2+1. The (2n)th reference cell includes a first terminal coupled to an (n+1)th bit line, and a second terminal coupled to the nth source line. The detection circuit compares a data current outputted from the data memory array and a reference current outputted from the reference memory array to determine a data state of a memory cell.

Memory device having reference memory array structure resembling data memory array structure, and methods of operating the same

A differential sensing device includes two reference cells, four path selectors, and four sample circuits. The first path selector is coupled to a first sensing node, the second reference cell, and a first memory cell. The second path selector is coupled to a second sensing node, the first reference cell, and the first memory cell. The third path selector is coupled to a third sensing node, the first reference cell, and a second memory cell. The fourth path selector is coupled to a fourth sensing node, the second reference cell, and the second memory cell. During a sample operation, the first sample circuit samples a first cell current, the second sample circuit samples the first reference current, the third sample circuit samples a second cell current, and the fourth sample circuit samples the second reference current.

Differential sensing device with wide sensing margin

A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.

Differential type sensing circuit with differential input and output terminal pair

A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Random bit cell with nonvolatile memory cell

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Charge pump circuit with low reverse current and low peak current

A high voltage driver includes a charge pump, a level shift circuit, a first string of diodes, and a second string of diodes. The charge pump adjusts a driving voltage according to a feedback voltage. The level shift circuit generates an output voltage according to the at least one control signal, and the level shift circuit includes a plurality of stacked transistors for relieving a high voltage stress caused by the driving voltage, and a plurality of control transistors coupled to the plurality of stacked transistors for controlling the output voltage. The first string of diodes provides a plurality of divisional voltages between the driving voltage and a reference voltage, and each of the stacked transistors has a control terminal receiving a corresponding divisional voltage of the plurality of divisional voltages. The second string of diodes provides the feedback voltage.

High voltage driver capable of preventing high voltage stress on transistors

A charge pump unit capable of reducing reverse current includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor. The first NMOS transistor and the first PMOS transistor are coupled in series and are controlled by a first clock signal. The second NMOS transistor and the second PMOS transistor are coupled in series and are controlled by a second clock signal. The first NMOS transistor is for receiving a first input voltage and the second NMOS transistor is for receiving a second input voltage. The first clock signal and the second clock signal transit at different time points. A rising edge of the first clock signal leads a respective falling edge of the second clock signal.

Charge pump circuit capable of reducing reverse currents

A charge pump system includes a logic circuit, a signal processing circuit, a charge pump circuit, a switching circuit, a first controllable discharge path, and a second controllable discharge path. The logic circuit receives a program enabling signal and generates a first control signal. The signal processing circuit receives a pump enabling signal, and generates a second control signal and a third control signal. The charge pump circuit receives the third control signal and generates an output signal. The switching circuit has a control terminal receiving the third control signal, a first terminal connected with the output terminal of the charge pump circuit, and a second terminal connected with a reservoir capacitor. The first controllable discharge path receives the first control signal, and the second controllable discharge path receives the second control signal.

Growing community of inventors

Hsinchu County, Taiwan

Cheng-Te Yang