Taiwan Semiconductor Manufacturing Comp. Ltd.

Silicon Integrated Systems Corporation

Cheng-Ta Wu

Yeur-Luen Tu

Chia-Shiung Tsai

Yu-Hung Cheng

Ting-Chun Wang

Shiu-Ko JangJian

Chii-Ming M Wu

Chih-Yu Lai

Wei-Ming You

Jiech-Fun Lu

Ru-Liang Lee

Kuo-Hwa Tzeng

Chih-Hui Huang

Shih-Pei Chou

Cheng-Wei Chen

Cheng-Yuan Tsai

Ching-Chun Wang

Shyh-Fann Ting

Xiaomeng Chen

Min-Ying Tsai

Tung-I Lin

Yu-Chun Chang

Kuan-Liang Liu

Wei-Li Chen

Chia-Ta Hsieh

Jhy-Jyi Sze

Yen-Chang Chu

Sen-Hong Syue

Cheng-Po Chau

Kun-Tzu Lin

Kuo Wei Wu

Ying Ling Tseng

Lan-Fang Chang

Sheng-Chau Chen

Lun-Kuang Tan

Wei-Kung Tsai

Chung-Ren Sun

Ming-Che Yang

Chung Chien Wang

Yong-En Syu

Chen-Cheng Chou

Shiu-Ko Jangjian

Yi-Hsien Lee

Chih-Hao Wang

Alexander Kalnitsky

Chih-Wei Lin

Chung-Yi Yu

Chun-Wei Chang

Neng-Kuo Chen

Yu-Lung Yeh

Po-Wei Liu

Victor Y Lu

Chen-Hao Chiang

Ming-Te Chen

Pu-Fang Chen

Tsung-Han Wu

Chih-Chien Wang

Chun-Han Tsao

Yen-Hsiu Chen

Eugene Chen

Luan Conn Tran

Po-Jung Chiang

Hong-Yi Wu

Shi-Chieh Lin

Xiao-Meng Chen

Liang-Yu Yen

Chris Chen

Jun-Jie Cheng

Yuan-Nien Chen

Yu-Ting Hsiao

Chiu Hua Chen

Yi-Fang Lee

Shu-Ju Tsai

Dun-Nian Yaung

Jen-Cheng Liu

Hsing-Lien Lin

Yu-Ting Lin

Feng-Jia Shiu

Shuang-Ji Tsai

Shih Pei Chou

Ching-Sen Kuo

U-Ting Chen

Chen-Fa Lu

Yao-Wen Hsu

Wang-Pen Mo

Kai-Chun Hsu

Wei-Chao Chiu

Kai Tzeng

Wen-Chi Lin

Yung-Hsiang Chan

Keng-Nan Chen

Chen Cheng Chou

Tung-Ting Wu

Alex Usenko

Po-Kai Hsiao

Tzu Kai Lin

Wei-Tung Huang

Po-Kang Ho

Yu-Hao Shih

Ming-Hsiang Kao

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Semiconductor-on-insulator (SOI) substrate and method for forming

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

RFSOI semiconductor structures including a nitrogen-doped charge-trapping layer and methods of manufacturing the same

Various embodiments of the present disclosure are directed towards an integrated chip including a first substrate having a front-side and a back-side opposite the front-side. A first doped region is in the first substrate and extends continuously from the front-side to the back-side. A conductive contact is over the first doped region. A conductive layer is between the first doped region and the conductive contact. The first doped region abuts a lower surface and sides of the conductive layer.

Conductive contact for ion through-substrate via

Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

Flat STI surface for gate oxide uniformity in Fin FET devices

The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Back-side deep trench isolation structure for image sensor

Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.

RF switch device with a sidewall spacer having a low dielectric constant

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Method for forming a semiconductor-on-insulator (SOI) substrate

In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Selective polysilicon growth for deep trench polysilicon isolation structure

A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

Method for manufacturing semiconductor structure

A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Strained gate semiconductor device having an interlayer dielectric doped with large species material

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer

Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Fabrication method of metal-free SOI wafer

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Shueishang, Taiwan

Cheng-Ta Wu