Cadence Design Systems, Inc.

Visualon, Inc.

Cheng-Ta Hsieh

Chih-Chang Lin

Yifeng Wang

Kuang-Chien Chen

Ming-Mao Chiang

Hyoheon Hong

Huan-Chih Tsai

Yung-Te Lai

Yubao Li

A system for providing video playback comprises a processor configured to synchronize clocks on the plurality of devices to a standard time, provide target video playback positions to the plurality of devices, wherein target video playback positions are based at least in part on the timing information, provide one or more locators for video streams to the plurality of devices, monitor playback status for each of the plurality of devices, and for a device, determine whether the playback status for the device indicates that a selected bitrate is too low or too high or that the playback is fast or slow; in response to determining the selected bitrate is too low, indicate to select a higher bitrate for a device; and in response to determining the selected bitrate is too high, indicate to select a lower bitrate for the device.

Synchronized video player

A system for providing video playback includes an interface and a processor. The interface is configured to receive a desired video playback request and receive a video content source switching request from a first video content source to a second video content source. The processor is configured to generate a not-all-I-frame first stream for the first video content source, generate an all-I-frame second stream and a not-all-I-frame second stream for the second video content source, switch from the not-all-I-frame first stream for the first video content source to the all-I-frame second stream for the second video content source, and switch from the all-I-frame second stream for the second video content source to the not-all-I-frame second stream for the second video content source on a next I-frame occurrence in the not-all-I-frame second stream for the second video content source.

Multiple view streaming

Some aspects provide determination of a function to rectify functional differences between netlist Gand netlist Ghaving inputs V. The determination may include determination of a signal s of netlist Gthat can be re-synthesized so as to correct the functional differences between netlist Gand netlist G, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist Gand netlist Gfor each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist Gand netlist Gfor each vector of inputs V in a case that s equals 1. Also included may be determination of whether the first function rectifies the functional differences between netlist Gand netlist G, assignment, if it is determined that the first function does not rectify the functional differences, of respective next values to the second plurality of inputs, and determination of a second function based on the first function, the assigned static values, the assigned next values, the first error function, and the second error function.

Determination of single-fix rectification function

A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.

Growing community of inventors

San Jose, CA, United States of America

Cheng-Ta Hsieh