Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Cheng-Lung Tsai

Ru-Gun Liu

Wen-Chun Huang

Tsong-Hua Ou

Ying-Chou Cheng

Sheng-Wen Lin

Ming-Hui Chih

Chia-Ping Chiang

Wen-Li Cheng

Yu-Po Tang

Josh J H Feng

Jui-Hsuan Feng

Chih-Wei Hsu

Tsai-Sheng Gau

Cheng-Cheng Kuo

Kuei-Liang Lu

Cheng Kun Tsai

Boren Luo

Cheng-Kun Tsai

Jeng-Shiun Ho

Wei-Long Wang

Bing-Syun Yeh

Mei-Nan Tsai

Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.

Polygon-based optical proximity correction

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Pattern recognition for integrated circuit design

The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

Practical approach to layout migration

The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Mask error enhancement factor (MEEF) aware mask rule check (MRC)

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Dissection splitting with optical proximity correction and mask rule check enforcement

An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.

Method, system, and apparatus for adjusting local and global pattern density of an integrated circuit design

The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.

Method of thermal density optimization for device and process enhancement

A heat dissipating device includes a heat dissipating fin unit, a heat dissipating fan unit, a heat exchanger, and a pump. The pump draws working fluid from the heat exchanger via a delivery pipe, and supplies the working fluid back to the heat exchanger via a supply pipe. The supply pipe is mounted on the heat dissipating fin unit such that the working fluid is cooled while passing through the supply pipe.

Heat dissipating device

Growing community of inventors

Hsin-Chu, Taiwan

Cheng-Lung Tsai