Chinese Academy of Sciences

International Business Machines Corporation

Cheng Lu

Ming Liu

Hangbing Lv

Qing Luo

Ling Li

Bing Chen

Guozhong Xing

Huai Lin

Zhong Su

Qi Liu

Jian Ye Chen

Rui Ma

Di Wang

Shenghua Bao

Changqing Xie

Xiaoxin Xu

Long Liu

Zuheng Wu

Peiwen Zhang

The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

Three-state spintronic device, memory cell, memory array and read-write circuit

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Complementary storage unit and method of preparing the same, and complementary memory

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Symmetric memory cell and BNN circuit

The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

Spintronic device, SOT-MRAM storage cell, storage array and in-memory computing circuit

The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

1S1R memory integrated structure with larger selector surface area which can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure and method for fabricating the same

A method and an apparatus for recommending information to users within a social network. The method builds a recommendation list with at least one two-tuple, where each two-tuple comprises a target user name and an information item and ranks the recommendation list by using two-tuples in the recommendation list as a basic unit. By selecting a two-tuple in the recommendation list, the user can recommend a corresponding information item to a user represented by a target user name. An apparatus is also provided by using a builder for building for a user a recommendation list comprising at least one two-tuple and a sorter for ranking the recommendation list by using two-tuples in the recommendation list as a basic unit, such that, by selecting a two-tuple in the recommendation list.

Method and apparatus for recommending information to users within a social network

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Beijing, China

Cheng Lu