Seiko Epson Corporation

Cheng-Long Tang

Derek J Lentz

Le Trong Nguyen

Te-Li Lau

Yasuaki Hagiwara

Yoshiyuki Miyayama

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Microprocessor architecture capable of supporting multiple heterogeneous processors

A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include a latch for storing a previous row address request, and a comparator for comparing a previously latched row address request with a present row address request associated with a specific device of the multiple devices seeking access to the MAU. The comparator asserts a row match signal when the previously latched row address request matches the present row address request. The system further includes an arbiter for controlling priorities associated with the multiple devices seeking access to the MAU. The arbiter increases a priority of the specific device when the row match signal is asserted

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. Selecting a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.

System and method for supporting a multiple width memory subsystem

A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes.

Microprocessor architecture with a switch network and an arbitration

System for supporting a buffer memory wherein data is stored in multiple

A system and method for eliminating the critical path of a processor-based system by sending a signal to transition memory and/or I/O control units to a READ/WRITE state prior to the end of the complete instruction decode. If the decoding phase of the opcode of the instruction reveals that a read-write step is to be carried out wherein memory or an I/O device must be accessed, the processor immediately sends a read-write request to the memory control unit and the I/O control unit prior to decoding the balance of the instruction. Once the balance of the instruction has been decoded and the access location is determined to be in either memory or an I/O device, a cancellation process takes place. In this cancellation process, if the access location is in memory, the I/O unit transitions from the read-write state to an idle state. If, however, the access destination is determined to be an I/O device, the memory control unit transitions from the read-write state to the idle state.

System and method for reducing the critical path in memory control unit

A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network and interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing the priority of the devices based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

Multi processor system having dynamic priority based on row match of

A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory are handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

Microprocessor architecture with a switch network for data transfer

The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. The use of a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.

System for transferring data onto buses having different widths

A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

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San Jose, CA, United States of America

Cheng-Long Tang