Macronix International Co., Ltd.

Cheng-Lin Chung

Nien-Chao Yang

Lai-Ching Lin

A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or &ldquo;1&rdquo;), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or &ldquo;0&rdquo;), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a &ldquo;0&rdquo; is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration. In another embodiment, the pull-up transistor is operated as a current mirror using a cell in a mini array. The first inverter of the data latch circuit can be used in the feedback path to the precharge transistor, or a separate feedback inverter can be provided.

High-speed sense amplifier with auto-shutdown precharge path

A flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns. The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line. The fourth of the bank-selecting switches is disposed between the ground line and the third sub-bit line. The fifth of the bank-selecting switch is disposed between the ground line and the third sub-bit line. The sixth bank-selecting switch is disposed between the ground line and the first sub-bit line. Wherein, the second, third, and fourth bank-selecting switches are controlled by a first selecting signal, and the first, fifth, and sixth bank-selecting switches are controlled by a second selecting signal.

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Hsinchu, Taiwan

Cheng-Lin Chung