Lsi Logic Corporation

Silicon Valley Research, Inc.

Cheng-Liang Ding

Ranko L Scepanovic

Ching-Yen Ho

Ting-Chi Wang

Jiabi J Zhu

Mary Jane Irwin

An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance S.sub.min from the obstacle is constructed until it reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Towards optimal Steiner tree routing in the presence of rectilinear

The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.

Integrated circuit layout

A large number of microelectronic circuit cells that are interconnected by a set of wiring nets are optimally placed on an integrated circuit chip such that all interconnects can be routed and the total wirelength of the interconnects is minimized. Cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells. This technique uses Rent's rule for combining pairs of neighboring clusters, and selects among pairs of clusters having the same Rent's exponent using distance information derived from global optimization processing. Clusters are prevented from growing to an excessive size by limiting the number of cells per cluster and the maximum area per cluster to predetermined maximum values. After the clusters are generated, they are placed using an optimization-driven placement technique, preferably 'Gordian'. Finally, the cells within each cluster are de-clustered and locally placed using a partitioning technique, preferably 'min-cut'.

Cell placement method for microelectronic integrated circuit combining

An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance s.sub.min from the. The lines are constructed until they reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Towards optimal steiner tree routing in the presence of rectilinear

An integrated circuit layout technique is described which employs an optimization-driven clustering technique to provide improved cell placement. The technique utilizes clustering of cells based upon Rent's rule, with global-optimization-derived inter-cell distances being used to break ties when identical Rent exponents are encountered. A constraint on the number of cells permitted to be in a cluster and a constraint on the maximum Rent exponent which to be considered for merging clusters minimize the 'overgrowth' of clusters and serve to even out cluster size, ideally suiting the technique to conventional partitioning and placement schemes.

Integrated circuit cell placement using optimization-driven clustering

An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance S.sub.min from the obstacle. The lines are constructed until they reach either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M. The solution to the problem of finding a Steiner tree for the escape graph also provides a suitable approximation of a Steiner tree for the original problem. This apparatus or method may be used to optimize the routing of conductive paths on integrated circuits.

Growing community of inventors

San Jose, CA, United States of America

Cheng-Liang Ding