Macronix International Co., Ltd.

Powerflash Technology Corporation

Cheng-Jye Liu

Chia-Hsing Chen

Tai-Liang Hsiung

Riichiro Shirota

Ching-Hsiang Hsu

Ming-Hung Chou

Jongoh Kim

Yi-Jin Kwon

Chun-Hsiung Hung

Han-Sung Chen

Ching-Sung Yang

Chen-Chin Liu

Jiunn-Ren Hwang

Tung-Cheng Kuo

Tseng-Yi Liu

Smile Huang

Lan-Ting Huang

Ruei-Ling Lin

A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes a charge trapping layer. The gates are disposed on the composite dielectric layer and across the conductive layers. Wherein, the conductive layers can be used as local bit lines to reduce the resistance values and improve the performance of the memory device.

Memory device and manufacturing method and operating method thereof

A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a status of at least one of the associated memory cells. The dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the associated memory cells.

Memory system with dynamic reference cell and method of operating the same

A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

Method for programming a memory structure

The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.

Mobile phone accessing system and related storage device

A read operation method is provided for a flash memory array having a plurality of memory cells, wordlines, even bitlines, odd bitlines and a plurality of bitline transistors. The method includes pre-charging the plurality of even bitlines to about Vcc/n and pre-charging the plurality of odd bitlines to ground. The current flowing to/from a first bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the first bit location in each of the memory cells. The method also includes pre-charging the plurality of odd bitlines to about Vcc/n and pre-charging the plurality of even bitlines to ground. The current flowing to/from a second bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the second bit location in each of the memory cells.

Decoding method in an NROM flash memory array

A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of sectors. The sector erase method includes erasing the memory cells of a first sector by applying successive erase pulses that increase in voltage magnitude or pulse width, until erasure of the first sector is verified. Erase condition information corresponding to the first sector, is recorded, this information including a number of times successive erase pulses are needed to be applied in order to erase the memory cells of the first sector. Memory cells of a next sector are erased by applying a first erase pulse having a voltage magnitude or pulse width determined from the recorded erase condition information. The first erase pulse may be incremented if the first erase pulse fails to erase that next sector.

Erase operation for use in non-volatile memory

A method for dynamically adjusting the operation of a memory chip is disclosed. First, a memory chip is provided. The memory chip comprises an ONO layer. Then, the thickness of the ONO layer in the memory chip is measured, and a read word line voltage of the memory chip is then adjusted based on the measured thickness of the ONO layer. Since the operation window of memory chip is dynamically adjusted, a more reliable product operation and a sufficient mass production window are obtained.

Method of dynamically adjusting operation of a memory chip and apparatus of measuring thickness of an ONO layer of the memory chip

A method for fabricating a nitride read-only memory is described. An ONO stacked layer and a protective layer are sequentially formed on a substrate. A patterning/etching process is performed to pattern the protective layer and the ONO stacked layer to expose a portion of the substrate. Thereafter, the protective layer is removed by using wet etching. An ion implantation is performed to form buried bit lines in the exposed substrate, and then an insulator is formed on each buried bit line. A plurality of word lines are formed on the substrate crossing over the buried bit lines.

Method for fabricating nitride read-only memory

A coding method of a multi-level cell, applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2 levels with respect to 2 codes. Each code is constructed with n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, the multi-level memory cell has a specified level for corresponding code to be stored. The relationship is a correspondence between the 2 codes and the 2 levels. Two codes corresponding to any neighboring two levels has only a one-bit difference.

Coding method of multi-level memory cell

A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed, wherein the the word line voltages are arbitrated according to the threshold voltages of the neighbor bits adjacent to the bits. Next, the bits, to which a same word line voltage should be applied, in the memory cells are distributed to a group of bits with the same word line voltage. Then, the same word line voltage is applied to the bits of the group of bits with the same word line voltage.

Method for compensating a threshold voltage of a neighbor bit

The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavy doping. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current require for Channel Hot Electron Injection (CHEI) programming. Furthermore, before erasing the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.

Method for operating a NROM device

A silicon nitride read only memory and associated method of data programming and erasing. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semiconductor substrate, a first type ion-doped gate conductive layer over the ONO layer and a second type ion doped source/drain region in the substrate on each side of the ONO layer, wherein the second type ions have an electrical polarity opposite to the first type ions. Data is programmed into the silicon nitride read only memory by channel hot electron injection and data is erased from the silicon nitride read only memory by negative gate channel erase method. Since the gate conductive layer and the channel layer are identically doped, the energy gap between the two layers reduced. Hence, operating voltage of the gate terminal is lowered and damage to the tunnel oxide layer by hot holes is reduced.

Silicon nitride read only memory structure and method of programming and erasure

The present invention provides a protection circuit comprising one diode wherein the diode is formed by diffusing a heavily doped material of a first conductivity type into a first region of a second conductivity type. An integrated circuit, such as a memory array, is coupled to the diode. The other diode back-to-back is coupled to the diode wherein the other diode is formed by diffusing a heavily doped material of the second conductivity type into the first region and a second region of the first conductivity type. The two diodes in series are capable of discharging for the memory array during manufacturing process.

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Hsinchu, Taiwan

Cheng-Jye Liu