United Microelectronics Corp.

Cheng-Ju Hsieh

Jacob Chen

Chian-Gauh Shih

Chien-Chung Pan

Jaris Yeh

A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

Power source design for embedded memory

A test pattern generator accompanying digital integrated circuits for successively generating a plurality of test patterns for a built-in self test. A plurality of shift registers are serially connected in a loop for successively outputting the test patterns in response to a clock signal. At least one logic gate is connected among the shift registers. At least one control means is connected within the loop. Using such a configuration, the shift registers are set to an initial pattern. The shift registers are then set to one of a plurality of test patterns. The test patterns are then successively output through the shift registers in response to the clock signal.

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Hsinchu Hsien, Taiwan

Cheng-Ju Hsieh