Taiwan Semiconductor Manufacturing Comp. Ltd.

Faraday Technology Corporation

Cheng-I Huang

Jung-Chan Yang

Ting-Wei Chiang

Chi-Yu Lu

Hui-Zhong Zhuang

Chung-Hsing Wang

Hsiang-Jen Tseng

Ni-Wan Fan

Stefan Rusu

Yi-Kan Cheng

Lipen Yuan

Ping-Hung Yuh

Li-Chun Tien

Shih-Chi Fu

Hsiao-Shu Chao

Chin-Hsiung Hsu

Sheng-Fang Cheng

Chen-Teng Fan

Wang-Jin Chen

Chih-Liang Chen

Lee-Chung Lu

Kuo-Nan Yang

Wen-Hao Chen

Huang-Yu Chen

Chin-Chang Hsu

Yen-Hung Lin

Hung Lung Lin

Ru-Gun Liu

Chin-Hsiang Lin

Chih-Ming Lai

Ching-Hua Hsieh

Shih-Ming Chang

Sheng-Hsiung Chen

Ken-Hsien Hsieh

Wen-Chun Huang

Yuan-Te Hou

Pin-Dai Sue

Chien-Wen Lai

Ching Fu Chang

Chi-Feng Lin

Yu-Wei Chou

Yu-Wen Tsai

Wen-Cheng Huang

Hsin-Yun Lin

Ya-Yun Liu

Jyh-Herny Wang

An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

Integrated circuit, system for and method of forming an integrated circuit

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Standard-cell layout structure with horn power and smart metal cut

A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Semiconductor device

A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Semiconductor device and layout thereof

An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

A semiconductor device, including: a first OD strip, a first doping region, a second OD strip, a second doping region, and a third doping region. The first OD strip extending in a first direction is disposed on the first OD strip, and includes a first-type dopant to define an active region of a first MOS. The second OD strip extending in the first direction and immediately adjacent to the first OD strip in a second direction, wherein the second direction is orthogonal with the first direction. The second doping region is disposed on the second OD strip, and includes a second-type dopant to define an active region of a second MOS. The third doping region is disposed on the second OD strip, and includes the second-type dopant and is configured to be a body terminal of the first MOS.

An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.

A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

Pattern formation method using a photo mask for manufacturing a semiconductor device

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.

A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.

A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

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Hsinchu, Taiwan

Cheng-I Huang