Realtek Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Cheng-Hung Wu

Yen-Chung Chen

Wen-Juh Kang

Yu-Chu Chen

Wen-Hsia Kung

Ji-Jan Chen

Tao Xu

Kuen-Jong Lee

Tsai-Ming Yang

Chun-Feng Liu

Cheng-Hua Wu

Bing-Juo Chuang

Yen-Ling Liu

Yu-Zuong Chou

Hui-Ling Lin

Yue-Cheng Zhao

Yung-Chieh Lo

James Lin

Wei-Cheng Lien

Chia-Liang Wei

Yue Cheng Zhao

Meng-Chih Hseir

Shan-Jie Wang

Hsiao-Pu Lin

A system on a chip (SoC) includes an on-screen display (OSD) circuit, a memory control circuit, and an audio processor. The OSD circuit is arranged to control OSD of a text message. The memory control circuit is coupled to a memory, and is arranged to read a text-to-speech (TTS) data corresponding to the text message from the memory. The audio processor is coupled to the memory control circuit, and includes a TTS circuit, wherein the TTS circuit is arranged to: receive the TTS data from the memory control circuit, and generate an audio output according to at least the TTS data.

System on a chip and display system

A display control integrated circuit (IC) applicable to performing multi-display processing in a display device includes multiple sub-circuits such as a Multi-Stream Transport (MST) stream splitting module, multiple video format conversion circuits, a multiplexer and a video combination module for generating a combined picture for being displayed. The display control IC may utilize at least one additional data path coupled to at least one predetermined sub-circuit among the multiple sub-circuits to obtain at least one signal, and output any signal of the at least one signal through a video output terminal of the display control IC and a video output port of the display device to be a video output signal for further use, where the at least one predetermined sub-circuit include at least one of the MST stream splitting module and the multiplexer.

Display control integrated circuit applicable to performing multi-display processing in display device

A video transmission method and a system thereof are provided. The video transmission method includes: obtaining a first display timing setting parameter of one or more display devices. A total transmission bandwidth of the display device is calculated according to the first display timing setting parameter, and when the total transmission bandwidth is greater than a maximum transmission bandwidth between a video source and a conversion device, a second display timing setting parameter with a lower bandwidth is generated corresponding to the first display timing setting parameter. The video source transmits a video signal conforming to the second display timing setting parameter to the conversion device. The conversion device converts the second display timing setting parameter of the video signal back to the first display timing setting parameter. The video signal conforming to the first display timing setting parameter is transmitted to the corresponding display device.

Video transmission method with adaptive adjustment bandwidth and system thereof

The present invention provides a DP to HDMI converter, wherein the DP to HDMI converter comprises a receiving circuit, a signal converter and a transmitter. In the operations of the DP to HDMI converter, the receiving circuit is configured to receive a plurality of input signals, wherein the input signals comprise a plurality of DP signals configured to generate an image frame with variable frame rate. The signal converter is configured to receive the plurality of input signals to generate a plurality of HDMI signals, wherein the signal converter includes a synchronization signal generator for generating a vertical synchronization signal and a horizontal synchronization signal of the plurality of HDMI signals according to a portion of the input signals. The transmitter is configured to output the plurality of HDMI signals.

DP to HDMI converter and associated signal conversion method

A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

Multi-channel transceiver

A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

Device and method for recovering clock and data

An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.

Unlock detector, unlock-detecting method and clock and data recovery circuit

A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.

Defect diagnosis

A method for fragmenting an incoming packet for transmission as a first outgoing packet and a second outgoing packet includes storing a payload of the incoming packet in a plurality of storage units beginning in a first storage unit, transmitting the first outgoing packet being formed according to a predetermined portion of the payload stored in the first storage unit, and after transmitting the first outgoing packet, transmitting the second outgoing packet being formed according to a remaining portion of the payload stored in the storage units.

Method for fragmenting an incoming packet into a first outgoing packet and a second outgoing packet

Growing community of inventors

Hsinchu, Taiwan

Cheng-Hung Wu