Taiwan Semiconductor Manufacturing Comp. Ltd.

Aiwan Semiconductor Manufacturing Company, Ltd.

Cheng Hung Lee

Hung-Jen Liao

Hong-Chen Cheng

Jonathan Tsung-Yung Chang

Chiting Cheng

Yangsyu Lin

Yu-Hao Hsu

Hau-Tai Shieh

Fu-An Wu

Jung-Ping Yang

Chen-Lin Yang

Chia-En Huang

Chih-Chieh Chiu

Chung-Ji Lu

Yen-Huei Chen

Chien-Yuan Chen

Ching-Wei Wu

Jui-Che Tsai

Hao-I Yang

Chien-Kuo Su

Derek C Tao

Pankaj Aggarwal

Chung-Yi Wu

Hsu-Shun Chen

Jhon Jhy Liaw

Shih-Lien Linus Lu

Wei Min Chan

Yi-Tzu Chen

Wei-Jer Hsieh

Hua-Hsin Yu

Tsung-Hsien Huang

Annie Lum

Po-Sheng Wang

Vineet Kumar Agrawal

Keun-Young Kim

Pyong Yun Cho

Kao-Cheng Lin

Chien-Chen Lin

Chien-Yu Huang

Chia-Chen Kuo

I-Han Huang

Che-Ju Yeh

Kuang Ting Chen

Chi-Kai Hsieh

Hektor Huang

Li-Chun Tien

Jung-Hsuan Chen

XiuLi Yang

Ming-Chien Tsai

Zhi-Hao Chang

Chun-Jiun Dai

Anjana Singh

Yi-Ching Chang

Hua-Tai Shieh

Chung-Cheng Chou

Kuo-Hua Pan

Chia-Cheng Chen

Chia-en Huang

Annie-Li-Keow Lum

Michael Patrick Clinton

Geng-Cing Lin

Shang-Chi Wu

Ming-Yi Lee

Hsiao-Lan Yang

Hsin-Hsin Ko

Bin-Hau Lo

Chung-Hsien Hua

Liangbo Zhuang

Hsiao-Tsung Yen

Shao-Yu Chou

Wun-Jie Lin

Chih-Yu Lin

Ho-Hsiang Chen

Chin-Wei Kuo

Yu-Ling Lin

Min-Chie Jeng

Mu-Jen Huang

He-Zhou Wan

Sahil Preet Singh

Li-Wen Wang

Kun-Lung Chen

Yi-Ju Chen

You-Cheng Xiao

Tsung-Yung Chang

Ming-En Bu

Simon Wang

Yen-huei Chen

Manish Arora

Yi-Hung Tsai

Fu-Chieh Hsu

Weiyang Jiang

Shi-Wei Chang

Wei-Shuo Kao

Ming-hung Chang

Li-Chen Chen

Hemant Patel

Chen-Li Yang

Ling-Chang Hu

Chung-Ji Liu

A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.

Memory device and method of operating the same

Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

I/O circuit design for SRAM-based PUF generators

A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Bit line pre-charge circuit and method

A device is provided and includes a sense amplifier and an output latch circuit. The sense amplifier adjusts voltage levels of first and second data lines according to a bypass data signal corresponding to a data signal in response to a first enable signal having a first logic state and a second enable signal having a second logic state different from the first logic state during a test mode. The output latch circuit generates a data output signal according to the voltage level of the first data line in response to the first enable signal having the second logic state and a third enable signal having the first logic state during the test mode.

Latch type sense amplifier for testing

The present disclosure provides a memory device, including a memory array, a tracking circuit, a memory controller, and a word line driver. A plurality of word lines are in communication with a plurality of memory cells of the memory array. The memory controller decodes a memory address of a memory access command to generate a decoded row address signal. The word line driver is configured to assert one of the plurality of word lines in response to the decoded row address signal. In response to detecting a switching event of a clock control signal derived from an input clock signal of the memory device, the memory controller asserts an tracking acceleration signal obtained from a tracking word line of the memory device to activate one or more first tracking arrays of the plurality of tracking arrays to pull down a voltage level of a tracking bit line.

Memory device and method for reducing active power consumption thereof using address control

A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Memory device with word line pulse recovery

A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Memory device sense amplifier control

A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Arrangements of memory devices and methods of operating the memory devices

A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Memory circuits with dynamically adjustable pulse widths and methods for operating the same

A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.

Latch circuit formed by modified memory cells

In some aspects of the present disclosure, a circuit in a first power domain is disclosed. In some aspects, the circuit in a first power domain includes a first enable-controlled logic gate coupled to a second circuit in a second power domain different from the first power domain. In some aspects, the circuit in a first power domain includes a feedback loop coupled to the first enable-controlled logic gate, the feedback loop including a first inverter and a second enable-controlled logic gate coupled to the first inverter. In some aspects, the circuit in a first power domain includes a second inverter coupled to the feedback loop.

Power loss regulation circuit

A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.

Memory circuit and method of operating same

A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Memory device and manufacturing method of the same

Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

Memory device and electronic device

A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

Was cell for SRAM high-R issue in advanced technology node

Growing community of inventors

Hsinchu, Taiwan

Cheng Hung Lee