Altera Corporation

Cheng-Hsiung Huang

Chih-Ching Shih

Yow-Juang Bill Liu

Hugh Sungki O

Jeffrey T Watt

Antonio Gallerano

Shuang Xie

Irfan Rahim

Shih-Lin S Lee

Stephanie T Tran

Guu Lin

Hugh Sung-Ki O

Wei-Guang Wu

Srinivas Perisetty

Albert Ratnakumar

Samit S Sengupta

Yowjuang (Bill) Liu

Kyle Bowers

Chiakang Sung

Shankar Sinha

Jeffrey Tyhach

Yowjuang Bill Liu

Yow-Juang (Bill) Liu

Billy Jow-Tai Kwong

Yu-Cheng Richard Gao

Yow-Juang B Lu

Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. Integrated circuits may include input-output pins that are coupled to the ESD protection circuitry. The ESD protection circuitry may include diode circuits, a control circuit, and a power clamp circuit. Each diode circuit may have a first terminal that is coupled to a respective input-output pin and a second terminal that is coupled to a shared ESD control line. The control circuit may supply a boosted voltage onto the control line to reverse bias the diode circuits during normal operation while the power clamp is turned off. During an ESD event, the power clamp may be turned on to sink current from the diode circuits. The power clamp may include a transistor having a substrate that is forward biased to improve transistor drive strength during the ESD event and that is reverse biased to reduce leakage during normal operation.

Electrostatic discharge protection circuitry with reduced capacitance

An electrostatic discharge (ESD) protection circuit includes an electrostatic discharge bus, first and second resistors coupled in series, first and second capacitors coupled in series, and first and second transistors. The first resistor is coupled to the electrostatic discharge bus. The first capacitor is coupled to the second resistor. The first transistor has a control input that is coupled between the first and the second resistors. The second transistor has a control input that is coupled between the first and the second capacitors.

Electrostatic discharge protection circuits and methods

A contact fuse is provided. The contact fuse includes a metal oxide semiconductor (MOS) transistor and a control circuit having outputs coupled to a plurality of terminals of the MOS transistor. The control circuit is operable to forward bias a body-source junction during a programming operation and operable to short the body-source junction during a sensing operation. A method of operating a contact fuse is also provided.

Contact fuse

An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.

Low-voltage programmable electrical fuses

An electrostatic discharge (ESD) protection structure comprising a polysilicon gate on an insulating layer on a substrate, said gate having first and second sides, a first heavily doped P-region in the substrate on the first side of the gate, a first heavily doped N-region in the substrate on the second side of the gate, and a shallow trench isolation isolating said first P-region and said first N-region from other structures in the substrate. In a first embodiment, the heavily doped regions are formed in a well having opposite conductivity to that of the substrate and a diode is formed at a PN junction between one of the heavily doped regions and the well. To minimize capacitance between the well and the substrate, the substrate is doped at a level of native doping and the well is isolated so that no other wells or heavily-doped regions are nearby in the substrate. Doping levels in the well and the dimensions of the gate are controlled to minimize on resistance (R) of the diode. In a second embodiment, no well is used.

Low capacitance, low on resistance ESD diode

Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.

Integrated circuits with nonvolatile memory elements

In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

Electrostatic discharge (ESD) protection device for use with multiple I/O standards

An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.

Electrostatic discharge protection in a field programmable gate array

A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.

Method and device for electrostatic discharge protection

A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.

I/O ESD protection device for high performance circuits

A conventional ESD protection circuit comprises an SCR and a first diode connected in series between ground and a node or pad to be protected and a second diode connected between ground and the node to be protected. An anode of the first diode and a cathode of the second diode are connected to the node to be protected. In one embodiment of the invention, the capacitance of the second diode is reduced by forming the second diode from a PN junction between a heavily doped region of one conductivity type and a substrate region instead of a well region of the opposite conductivity type. The reduction in the capacitance of the second diode makes it possible to increase the size of the first diode and SCR, thereby decreasing their resistance, while keeping the total capacitance of the ESD circuit at or below the capacitance of the prior art ESD circuit. A second embodiment of an ESD protection comprises an SCR and a first diode connected in series between ground and node to be protected and second and third diodes connected in series between ground and the node to be protected with the anode of the second diode connected to ground. Again, the capacitance of the second diode is reduced by forming the diode from a PN junction between a heavily doped region of one conductivity type and a substrate region of the other conductivity type.

Low capacitance ESD protection structure for high speed input pins

A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.

Growing community of inventors

Cupertino, CA, United States of America

Cheng-Hsiung Huang