Mediatek Corporation

Faraday Technology Corporation

Industrial Technology Research Institute

Cheng-Hsing Chien

Sheng-Hua Chen

Yu-Hao Liu

Yung-Chieh Yu

Jia-Yi Xu

Hugh Thomas Mair

Chia-Wei Wang

Hwang-Cherng Chow

Yi-Te Chiu

Uming Ko

Lee-Kee Yong

Che-Wei Wu

A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

D flip-flop

A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Dual-rail power equalizer

The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Flip-flop for low swing clock signal

In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VDD, to a second device having a second voltage, such as VCC, through a terminal pad. The buffer includes a first driver for driving a terminal pad up to the first voltage, wherein the first driver preferably includes a pair of in series PMOS transistors formed in an n floating well. The buffer further includes a second driver for driving the terminal pad down to a voltage VSS. Such a structure provides a simple circuit that requires only a single terminal pad, a single power supply, and is substantially free of dc leakage currents.

Bidirectional buffer with active pull-up/latch circuit for mixed-voltage

Growing community of inventors

Hsinchu, Taiwan

Cheng-Hsing Chien