Global Unichip Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Hong Tsai

Min-Hsiu Tsai

Chien-Cheng Wu

Hsin-Hsiung Liao

Chih-Mou Tseng

Yen-Chih Chiu

Teng-Nan Liao

Sin-Huei Li

Hu-Cheng Jiang

Yih-Chih Chou

Te-Hsun Fu

Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.

Chip power consumption analyzer and analyzing method thereof

A computer executing method is provided in this disclosure. The computer executing method is configured for synthesizing a clock tree circuit, the clock tree circuit includes a plurality of clock pins, a plurality of weight values are set between any of the clock pins, the computer executing method includes steps of: establishing a graph model; utilizing a force directed algorithm to calculate a branch position according to the weight values and a position of the clock pins; setting a guide buffer in the branch position and updating a netlist; performing a clock tree synthesis (CTS) and executing a post-CTS static timing analysis (STA); determining whether an analysis result of the post-CTS STA and a timing setup value is identical or not; and if the analysis result does not match the timing setup value, re-establishing a graph model.

Computer executing method, clock data processing system and computer readable storage medium

A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.

Timing analysis method for digital circuit design and system thereof

In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.

System and method for optimizing logic timing

Growing community of inventors

Hsinchu, Taiwan

Cheng-Hong Tsai