Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Anpec Electronics Corporation

Candor Ltd.

Institution of Occupational Safety and Health

Cheng-Han Wu

Ching-Yu Chang

Chin-Hsiang Lin

Tzu-Yang Lin

Ming-Hui Weng

Chen-Yu Liu

Siao-Shan Wang

Kuei-Ming Chang

Rei-Jay Hsieh

Chie-Iuan Lin

Keng-Chu Lin

Joung-Wei Liou

Ya Hui Chang

Tsai-Hao Hung

Fu-Chuan Chen

Ping-Cheng Ko

Jyh-Huei Chen

Heng-Jen Lee

Chun-Chi Yu

Shih-Che Wang

Ho-Yung David Hwang

Wen-Zhan Zhou

Ya-Ching Chang

Yu-Chen Huang

Hsu-Yuan Liu

Jhon-Jhy Liaw

Chao-Cheng Chen

Ryan Chia-Jen Chen

Hsin-Yu Chen

Shou-Wei Hsieh

Chun-Hao Lin

Wen-Yun Wang

Fang-yu Liu

Chih-Ming Su

Eric Chih-Fang Liu

Yi-Ren Chen

Yu-Ho Chiang

Yuan-Ting Chuang

Fang-Yu Liu

Chien-Chih Chen

Yu Chao Lin

Yu-Chao Lin

Wei-Han Lai

Cheng-Guo Chen

Kuo-Shu Tseng

Wen-Huei Guo

Yu-Chung Su

Yuan-Chi Pai

Ta-Kang Lo

Chuen-Jinn Tsai

Tung-Sheng Shih

Chien-Chih Huang

Chen Yi Hsu

Shang-Sheng Li

Hung-Yi Wu

Yu-Wei Lee

Tse-Hsu Wu

Yun-Chiang Chang

Yu-Cheng Chang

Wen-Pin Hsu

Chie-luan Lin

Yong-Fa Huang

Shi-Nian Uang

Jian-Li Lin

Kuo-Chiang TIng

Ting-Hui Kao

Chih-Hao Hsu

Hsuan-Hung Liu

Jen-How Wang

Chi-Kang Chen

The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, portions of an adhesion layer, barrier layer and/or seed layer is protected by a layer of an organic mask material as portions of the adhesion layer, barrier layer and/or seed layer are removed. The layer of organic mask material is modified to improve its resistance to penetration by wet etchants used to remove exposed portions of the adhesion layer, barrier layer and/or seed layer. An example modification includes treating the layer of organic mask material with a surfactant that is absorbed into the layer of organic mask material.

Treatment of spin on organic material to improve wet resistance

A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Photoresist and method of formation and use

A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

High-electron mobility transistor and method for fabricating the same

Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Semiconductor processing apparatus and method utilizing electrostatic discharge (ESD) prevention layer

A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Semiconductor device

A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Lithography method for positive tone development

Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

Method composition and methods thereof

A power converter having a multi-slope compensation mechanism is provided. A multi-slope compensation circuit of the power converter includes a plurality of first capacitors, a comparator and a plurality of first resistors. A first terminal of each of the plurality of first capacitors and a node between a second terminal of a high-side switch and a first terminal of a low-side switch are connected to an inductor. A plurality of first input terminals of a comparator are respectively connected to second terminals of the plurality of first capacitors, and are respectively connected to first terminals of the plurality of first resistors. Second terminals of the plurality of first resistors are coupled to a second reference voltage. A second input terminal of the comparator is coupled to a first reference voltage. An output terminal of the comparator is connected to an input terminal of a driver circuit.

Power converter having multi-slope compensation mechanism

A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

System and method for supplying and dispensing bubble-free photolithography chemical solutions

A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Integrated circuit structure

A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.

Liquid storage for facility chemical supply system

A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

Power converter having slew rate controlling mechanism

An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

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Taichung, Taiwan

Cheng-Han Wu