United Microelectronics Corp.

Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Han Huang

Yung-Chih Chen

Water Lur

Mao-Hsun Cheng

Ching-Sheng Cheng

Meng-Jin Tsai

Chun-Da Tu

Hsiang-Sheng Chang

Chen-Chiu Hsue

Kai-Wei Hong

Chuang-Cheng Yang

Kuang-Hua Wang

Jian-Ting Chen

Gary Y Hong

Ming-Tzong Yang

Jih-Wen Chou

Chih-Lung Lin

Wei-Hsuan Chang

Chen-Chi Lin

Cheng-Yeh Tsai

Po-Hung Chen

Mei-Sheng Ma

Chia-Che Hung

Hsiao-Chung Cheng

Meng-Sheng Chang

Chen-Wei Lee

Shih-Chanh Chang

Yi-Chiung Chen

Po-Cheng Lai

Wei-Ting Wu

Po-Jung Wu

Cheng-Jung Hsu

Te-Chuan Liao

Liang-Chih Lin

A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

Testing apparatus and method of using the same

A pixel structure includes a light-emitting module, multiple sub-pixel circuits, and an internal driving circuit. The light-emitting module includes multiple sub-pixel light-emitting elements, and is disposed on a first plane. The multiple sub-pixel circuits are disposed on a second plane, and each of the multiple sub-pixel circuits is electrically connected with a corresponding one of the multiple sub-pixel light-emitting elements. The internal driving circuit is disposed on the second plane, and is electrically connected with one of the multiple sub-pixel circuits. The first plane is different from the second plane, and the multiple sub-pixel circuits and the internal driving circuit are located in a vertical projection projected by the light-emitting module onto the second plane.

Pixel structure and display panel

A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.

Shift register circuit and gate driver

A pixel driving circuit utilizing a transistor having two gate ends as the driving unit for pixels of a display panel to provide a stable driving current to compensate for the variation of threshold voltages of transistors in different pixels and to improve the uniformity of the brightness of the display panel.

Pixel driving circuit and operating method thereof

A pixel structure includes a first TFT, an adhesive layer, an LED, and a detection conductive layer. The first TFT is coupled to a conductive layer and is configured to transmit display data to the conductive layer. The adhesive layer covers the conductive layer. The LED is disposed on the adhesive layer. The detection conductive layer is disposed on the adhesive layer, and the detection conductive layer, the adhesive layer, and the conductive layer constitute a detection capacitor. Here, a thickness of the detection conductive layer is equal to or slightly greater than a height of the LED.

Pixel structure

A display device has a substrate for disposing a display area having an array of pixels, and control circuits having shift registers and latches to provide image data and timing control signals to the pixels. The control circuits have signal lines electrically connected to a connection cable to receive therefrom data signals indicative of the image data and timing pulses indicative of the timing control signals. The connection cable is also configured to provide reference signals to the shift registers and latches in the control circuits. The data signals are digital signals having an amplitude range greater than the amplitude range of the reference signals. No driver IC is disposed on the substrate to process analog signals. Each of the pixels has three sub-pixels and each of the color sub-pixels has three color sub-areas configured to receive timing control signals from a different scan line.

Display device without a driver IC

A display panel and a compensation circuit are provided. The display panel has a periphery region and a display region. The display panel includes pixel columns and a threshold voltage compensation circuit. The pixel columns are disposed in the display region. The threshold voltage compensation circuit is disposed in the periphery region. The threshold voltage compensation circuit receives a compensation voltage, outputs threshold voltage information of a compensation transistor based on the compensation voltage, and generates compensated display data based on the threshold voltage information and display data.

Compensation circuit and display panel

A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Shift register

A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Touch display apparatus and shift register thereof

An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level.

Resetting circuit

A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width. The method features a two-step etching process in which the first etching process is performed to form one spacer structure to the first desired width, while the second etching process is performed to form the other spacer structure to the second desired width.

Method of forming separated spacer structures in mixed-mode integrated circuits

A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

Method for manufacturing mixed-mode devices

A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.

Method of fabricating dual voltage MOS transistors

A method for forming a double spacer structure comprising the steps of first providing a semiconductor substrate that has a first gate and a second gate already formed thereon, wherein the gate length of the second gate is greater than the gate length of the first gate. Then, a first insulating layer is formed over the substrate and the gates. Next, a photoresist layer is formed over the first insulating layer above the second gate while exposing the first insulating layer above the first gate. Subsequently, a first etching operation is performed to establish a first spacer structure along the sidewalls of the first gate, and then the photoresist layer is removed leaving the first insulating layer over the second gate. Thereafter, a second insulating layer is formed over the substrate, the first gate and the first insulating layer, and then a second etching operation is performed to establish a second spacer structure along the sidewalls of the second gate. Therefore, a second spacer that has a width greater than the first spacer does is finally obtained.

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Hsin-Chu, Taiwan

Cheng-Han Huang