Altera Corporation

Cheng H Huang

Hugh Sung-Ki O

Chih-Ching Shih

Yowjuang (Bill) Liu

Yowjuang William Liu

Yow-Juang Bill Liu

Chiakang Sung

Jeffrey T Watt

Irfan Rahim

John C Costello

Yow-Juang (Bill) Liu

The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

ESD protection device for high performance IC

An integrated circuit (IC) includes a multiple-finger transistor structure. The multiple-finger transistor structure includes one transistor configured as a ballasted device. The multiple-finger transistor structure further includes a second transistor configured as a trigger device for the ballasted device.

Apparatus and methods for electrostatic discharge circuitry with snap-back device

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

Electrically-programmable transistor antifuses

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Electrically-programmable integrated circuit antifuses

The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small NP diode or a PN diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

Methods of fabricating ESD protection structures

A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.

Technique for protecting integrated circuit devices against electrostatic discharge damage

The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N P diode or a P N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N&plus; (or P&plus;) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

Growing community of inventors

Cupertino, CA, United States of America

Cheng H Huang