Taiwan Semiconductor Manufacturing Comp. Ltd.

Atop Technologies Inc.

Cheng-Chung Lin

Chung-Shi Liu

Chien Ling Hwang

Sang Hoo Dhong

Ming-Zhang Kuo

Chia-Hui Lin

Baw-Ching Perng

Ai-Sen Liu

Ming-Ta Lei

Ying-Jui Huang

Ping-Lin Yang

Yih-Shung Lin

Ming-Da Cheng

Osamu Takahashi

Wen-Kai Wan

Yi-Wen Wu

Meng-Wei Chou

Ho-Chieh Hsieh

Kuo Cheng Lin

Chen-Hua Douglas Yu

Syun-Ming Jang Jang

Lee-Chung Lu

Hsiu-Jen Lin

Wen-Hsiung Lu

Ming-Che Ho

Shang-Chih Hsieh

Chun-Cheng Lin

Jerry Chang Jui Kao

Chi-Lin Liu

Cheng-Ting Chen

Kuei-Wu Huang

De-Yuan Lu

Zheng-Yi Lim

Hsueh-Chih Chou

Chia Hao Tu

Yih-Hsiung Lin

Kuo Feng Tseng

Jimmy Hsiao

Hui-Zhong Zhuang

Li-Chun Tien

Tien-I Bao

Ta-Pen Guo

Hui-Jung Tsai

Kuei-Wei Huang

Lain-Jong Li

Ai-Tee Ang

Yi-Yang Lei

Tsai-Tsung Tsai

Jia-Rong Hsu

Chun-Hui Huang

Kuo-Feng Tseng

Chih-Lung Liu

Sang-Hoo Dhong

Chung-Sui Liu

Hsien-Min Hsu

Ming-Dai Lei

Lain-Jang Li

A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

System and method of timing characterization for semiconductor circuit

A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.

Method for cell placement in semiconductor layout and system thereof

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Integrated circuit with well and substrate contacts

One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.

Scan cell assignment

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Pillar bumps and process for making same

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Electron beam lithography methods including time division multiplex loading

A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.

Clock regenerator

A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.

Memory circuit for pre-charging and write driving

A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.

Method of making a conductive pillar bump with non-metal sidewall protection structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

System and method for fine pitch PoP structure

A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Charged particle lithography system with a long shape illumination beam

The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Electron beam lithography systems and methods including time division multiplex loading

A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.

Fine-pitch package-on-package structures and methods for forming the same

This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

Copper pillar bump with non-metal sidewall protection structure and method of making the same

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Taipei, Taiwan

Cheng-Chung Lin