Sandisk Technologies Inc.

Cheng-Chung Chu

Masaaki Higashitani

Jayavel Pachamuthu

Tuan Duc Pham

Fumitoshi Ito

Raghuveer S Makala

Yanli Zhang

Fei Zhou

Yao-Sheng Lee

Daniel Joseph Linnen

Jongsun Sel

Kensuke Yamaguchi

Ashish Ghai

Masanori Terahara

Yusuke Ikawa

Shuji Minagawa

Fabo Yu

Tsuyoshi Sendoda

Kei Samura

Seyyed Ehsan Esfahani Rashidi

Janet George

Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Implementation of deep neural networks for testing and quality control in the production of memory devices

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Virtual metrology for feature profile prediction in the production of memory devices

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

Offset backside contact via structures for a three-dimensional memory device

Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.

Inter-plane offset in backside contact via structures for a three-dimensional memory device

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Milpitas, CA, United States of America

Cheng-Chung Chu