Genesys Logic, Inc.

Cheng-Chih Yang

Tei-Wei Kuo

Jen-Wei Hsieh

Yuan-hao Chang

Chin-hsien Wu

Yuan-sheng Chu

Po-Liang Wu

A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Method for performing static wear leveling on flash memory

A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory. Further, the management method operates and maintains the physical memory sets, the physical memory blocks, and the logical blocks at a set level so that the utilization rate of random access memory is reduced to decrease the access capacity of the random access memory while operating the physical memory blocks and the logical blocks of the flash memory.

Management method for reducing utilization rate of random access memory (RAM) used in flash memory

A cache device comprises a hard disk, cache control unit and at least one flash memory, whereby the cache control unit controlling and regulating the flash memory as the hard disk cache device. The present invention method is defined by setting up a management table to manage each corresponding logical block address of the flash memory through a cache data read-out step and cache data write-in step in order to manage the cache read or write action of the flash memory on the hard disk. In addition, the step of recycling a cache space and replacing cache temporary data storage is to remove and replace temporary cache and storage space within the flash memory on the hard disk. Moreover, the step of reconstruction management table is provided to reconstruct management table loss or damage caused by power outage or irregular shut-down of the computer and will be able to provide flash memory on the hard disk cache control.

Device and method for using a flash memory as a hard disk cache

A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.

Flash translation layer apparatus

A method and an apparatus for dynamically configuring the redundant areas of a non-volatile memory is provided wherein each page of a memory is configured into a plurality of data areas and a plurality of redundant areas. The redundant areas interleave the data areas, or are arranged behind any data area. The system information and the status information is programmed into each data area of the page according to the original status information, so as to allow the flash drive to load a data area and an associated redundant area for each access operation with a smaller buffer.

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Taipei, Taiwan

Cheng-Chih Yang