United Microelectronics Corp.

United Silicon Incorporated

Cheng-Chih Kung

Shing-Ren Sheu

Cheng-Tzung Tsai

Peter Chou

Terry Chung-Yi Chen

Cheng-Chieh Huang

Yu-Chih Chuang

Lien-Sheng Chung

Da-Wen Hsia

Nai-Jen Yeh

Che-Pin Tseng

Tai-Yuan Li

A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

Variable work function transistor high density mask ROM

A method is disclosed for removing pad nodules. The method provides a wafer comprising pads and pad nodules which are formed on said pads, wherein said pads are made from a metal selected from the group consisting of aluminum and an aluminum-copper alloy. Then, the method dips the wafer into deionized water for removing the pad nodules. Thereafter, the method spin-dries the wafer and coats an alkaloid developer on the wafer for further removing the pad nodules. Finally, the method removes the alkaloid developer from the wafer and bakes the wafer.

Method for removing pad nodules

A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.

Method for forming a capacitor having selective hemispherical grained polysilicon

A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.

Short turn around time mask ROM process

A fabricating method for a DRAM capacitor is provided. A DRAM is formed on a substrate, wherein a transistor has been formed. A first oxide layer is formed over the substrate and a contact window is formed on the first oxide layer to expose a source region of the transistor. Then, a bit line is formed in the contact window, wherein the bit line is connected to the source region of the transistor. A second oxide layer is formed on the bit line and the first oxide layer. Then, a third oxide layer is formed on the second oxide layer. A second contact window is further defined to expose a drain region of the transistor, wherein the drain region has a native oxide layer formed on it. Next, a first polysilicon film is formed on the exposed drain region of the second contact window. A high dosage implantation is used to remove the native oxide layer. Then, a second polysilicon layer is formed over the substrate. Finally, the finishing process followed is performed to complete the fabrication of a DRAM capacitor.

Method of fabricating DRAM capacitor

A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.

Growing community of inventors

Hsin-Chu, Taiwan

Cheng-Chih Kung